Lines Matching +full:0 +full:x01f80000
23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
39 #define AR_PHY_FC_TURBO_MIMO 0x00000004 /* Set turbo for mimo mode */
41 #define AR_PHY_TIMING3 0x9814 /* Timing control 3 */
42 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
44 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000
47 #define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */
48 #define AR_PHY_CHIP_ID_REV_2 0x42 /* 5212 Rev 2 BB w. TPC fix */
49 #define AR_PHY_CHIP_ID_REV_3 0x43 /* 5212 Rev 3 5213 */
50 #define AR_PHY_CHIP_ID_REV_4 0x44 /* 5212 Rev 4 2313 and up */
52 #define AR_PHY_ACTIVE 0x981C /* activation register */
53 #define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */
54 #define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */
56 #define AR_PHY_TX_CTL 0x9824
57 #define AR_PHY_TX_FRAME_TO_TX_DATA_START 0x0000000f
58 #define AR_PHY_TX_FRAME_TO_TX_DATA_START_S 0
60 #define AR_PHY_ADC_CTL 0x982C
61 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
62 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
63 #define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
64 #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 /* BB Rev 4.2+ only */
65 #define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 /* BB Rev 4.2+ only */
66 #define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
69 #define AR_PHY_BB_XP_PA_CTL 0x9838
70 #define AR_PHY_BB_XPAA_ACTIVE_HIGH 0x00000001
71 #define AR_PHY_BB_XPAB_ACTIVE_HIGH 0x00000002
74 #define AR_PHY_TSTDAC_CONST 0x983C
75 #define AR_PHY_TSTDAC_CONST_Q 0x0003FE00
77 #define AR_PHY_TSTDAC_CONST_I 0x000001FF
79 #define AR_PHY_SETTLING 0x9844
80 #define AR_PHY_SETTLING_AGC 0x0000007F
81 #define AR_PHY_SETTLING_AGC_S 0
82 #define AR_PHY_SETTLING_SWITCH 0x00003F80
85 #define AR_PHY_RXGAIN 0x9848
86 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
88 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
91 #define AR_PHY_DESIRED_SZ 0x9850
92 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF
93 #define AR_PHY_DESIRED_SZ_ADC_S 0
94 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
96 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
99 #define AR_PHY_FIND_SIG 0x9858
100 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
102 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
105 #define AR_PHY_AGC_CTL1 0x985C
106 #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
108 #define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
111 #define AR_PHY_AGC_CONTROL 0x9860 /* chip calibration and noise floor setting */
112 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
113 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calculation */
114 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* Enable noise floor calibration to happen */
115 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* Allow Filter calibration */
116 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* Don't update noise floor automatically */
118 #define AR_PHY_SFCORR_LOW 0x986C
119 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
120 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
122 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
124 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
127 #define AR_PHY_SFCORR 0x9868
128 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
129 #define AR_PHY_SFCORR_M2COUNT_THR_S 0
130 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
132 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000
135 #define AR_PHY_SLEEP_CTR_CONTROL 0x9870
136 #define AR_PHY_SLEEP_CTR_LIMIT 0x9874
137 #define AR_PHY_SLEEP_SCAL 0x9878
139 #define AR_PHY_PLL_CTL 0x987c /* PLL control register */
140 #define AR_PHY_PLL_CTL_40 0xaa /* 40 MHz */
141 #define AR_PHY_PLL_CTL_44 0xab /* 44 MHz for 11b, 11g */
142 #define AR_PHY_PLL_CTL_44_5112 0xeb /* 44 MHz for 11b, 11g */
143 #define AR_PHY_PLL_CTL_40_5112 0xea /* 40 MHz for 11a, turbos */
144 #define AR_PHY_PLL_CTL_40_5413 0x04 /* 40 MHz for 11a, turbos with 5413 */
145 #define AR_PHY_PLL_CTL_HALF 0x100 /* Half clock for 1/2 chan width */
146 #define AR_PHY_PLL_CTL_QUARTER 0x200 /* Quarter clock for 1/4 chan width */
148 #define AR_PHY_BIN_MASK_1 0x9900
149 #define AR_PHY_BIN_MASK_2 0x9904
150 #define AR_PHY_BIN_MASK_3 0x9908
152 #define AR_PHY_MASK_CTL 0x990c /* What are these for?? */
153 #define AR_PHY_MASK_CTL_MASK_4 0x00003FFF
154 #define AR_PHY_MASK_CTL_MASK_4_S 0
155 #define AR_PHY_MASK_CTL_RATE 0xFF000000
158 #define AR_PHY_RX_DELAY 0x9914 /* analog pow-on time (100ns) */
159 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
161 #define AR_PHY_TIMING_CTRL4 0x9920 /* timing control */
162 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */
163 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */
164 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */
166 #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */
167 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithm…
169 #define AR_PHY_TIMING_CTRL4_DO_IQCAL 0x10000 /* perform IQ calibration */
170 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 /* Enable spur filter */
171 #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
172 #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
174 #define AR_PHY_TIMING5 0x9924
175 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
178 #define AR_PHY_PAPD_PROBE 0x9930
179 #define AR_PHY_PAPD_PROBE_POWERTX 0x00007E00
181 #define AR_PHY_PAPD_PROBE_NEXT_TX 0x00008000 /* command to take next reading */
182 #define AR_PHY_PAPD_PROBE_TYPE 0x01800000
184 #define AR_PHY_PAPD_PROBE_TYPE_OFDM 0
186 #define AR_PHY_PAPD_PROBE_GAINF 0xFE000000
189 #define AR_PHY_POWER_TX_RATE1 0x9934
190 #define AR_PHY_POWER_TX_RATE2 0x9938
191 #define AR_PHY_POWER_TX_RATE_MAX 0x993c
192 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
194 #define AR_PHY_FRAME_CTL 0x9944
195 #define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
197 #define AR_PHY_FRAME_CTL_ERR_SERV 0x20000000
199 #define AR_PHY_FRAME_CTL_EMU_M 0x80000000
201 #define AR_PHY_FRAME_CTL_WINLEN 0x00000003
202 #define AR_PHY_FRAME_CTL_WINLEN_S 0
204 #define AR_PHY_TXPWRADJ 0x994C /* BB Rev 4.2+ only */
205 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
207 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
210 #define AR_PHY_RADAR_0 0x9954 /* radar detection settings */
211 #define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */
212 #define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */
214 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */
216 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */
218 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */
220 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */
224 #define AR_PHY_RADAR_2 0x9958 /* radar detection settings */
225 #define AR_PHY_RADAR_2_ENRELSTEPCHK 0x00002000 /* Enable using max rssi */
226 #define AR_PHY_RADAR_2_ENMAXRSSI 0x00004000 /* Enable using max rssi */
227 #define AR_PHY_RADAR_2_BLOCKOFDMWEAK 0x00008000 /* En block OFDM weak sig as radar */
228 #define AR_PHY_RADAR_2_USEFIR128 0x00400000 /* En measuring pwr over 128 cycles */
229 #define AR_PHY_RADAR_2_ENRELPWRCHK 0x00800000 /* Enable using max rssi */
230 #define AR_PHY_RADAR_2_MAXLEN 0x000000FF /* Max Pulse duration threshold */
231 #define AR_PHY_RADAR_2_MAXLEN_S 0
232 #define AR_PHY_RADAR_2_RELSTEP 0x00001F00 /* Pulse relative step threshold */
234 #define AR_PHY_RADAR_2_RELPWR 0x003F0000 /* pulse relative power threshold */
237 #define AR_PHY_SIGMA_DELTA 0x996C /* AR5312 only */
238 #define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
239 #define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
240 #define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
242 #define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
244 #define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
247 #define AR_PHY_RESTART 0x9970 /* restart */
248 #define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */
251 #define AR_PHY_RFBUS_REQ 0x997C
252 #define AR_PHY_RFBUS_REQ_REQUEST 0x00000001
254 #define AR_PHY_TIMING7 0x9980 /* Spur mitigation masks */
255 #define AR_PHY_TIMING8 0x9984
256 #define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
257 #define AR_PHY_TIMING8_PILOT_MASK_2_S 0
259 #define AR_PHY_BIN_MASK2_1 0x9988
260 #define AR_PHY_BIN_MASK2_2 0x998c
261 #define AR_PHY_BIN_MASK2_3 0x9990
262 #define AR_PHY_BIN_MASK2_4 0x9994
263 #define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
264 #define AR_PHY_BIN_MASK2_4_MASK_4_S 0
266 #define AR_PHY_TIMING9 0x9998
267 #define AR_PHY_TIMING10 0x999c
268 #define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
269 #define AR_PHY_TIMING10_PILOT_MASK_2_S 0
271 #define AR_PHY_TIMING11 0x99a0 /* Spur Mitigation control */
272 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
273 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
274 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
276 #define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
277 #define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
279 #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
281 #define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */
282 #define AR_PHY_REFCLKDLY 0x99f4
283 #define AR_PHY_REFCLKPD 0x99f8
286 #define AR_PHY_IQCAL_RES_PWR_MEAS_I 0x9c10 /* power measurement for I */
287 #define AR_PHY_IQCAL_RES_PWR_MEAS_Q 0x9c14 /* power measurement for Q */
288 #define AR_PHY_IQCAL_RES_IQ_CORR_MEAS 0x9c18 /* IQ correlation measurement */
290 #define AR_PHY_CURRENT_RSSI 0x9c1c /* rssi of current frame rx'd */
292 #define AR_PHY_RFBUS_GNT 0x9c20
293 #define AR_PHY_RFBUS_GNT_GRANT 0x1
295 #define AR_PHY_PCDAC_TX_POWER_0 0xA180
298 #define AR_PHY_MODE 0xA200 /* Mode register */
299 #define AR_PHY_MODE_QUARTER 0x40 /* Quarter Rate */
300 #define AR_PHY_MODE_HALF 0x20 /* Half Rate */
301 #define AR_PHY_MODE_AR5112 0x08 /* AR5112 */
302 #define AR_PHY_MODE_AR5111 0x00 /* AR5111/AR2111 */
303 #define AR_PHY_MODE_DYNAMIC 0x04 /* dynamic CCK/OFDM mode */
304 #define AR_PHY_MODE_RF2GHZ 0x02 /* 2.4 GHz */
305 #define AR_PHY_MODE_RF5GHZ 0x00 /* 5 GHz */
306 #define AR_PHY_MODE_CCK 0x01 /* CCK */
307 #define AR_PHY_MODE_OFDM 0x00 /* OFDM */
308 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x100 /* Disable dynamic CCK detection */
310 #define AR_PHY_CCK_TX_CTRL 0xA204
311 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
313 #define AR_PHY_CCK_DETECT 0xA208
314 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
315 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
316 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
318 #define AR_PHY_GAIN_2GHZ 0xA20C
319 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
322 #define AR_PHY_CCK_RXCTRL4 0xA21C
323 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
326 #define AR_PHY_DAG_CTRLCCK 0xA228
327 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 /* BB Rev 4.2+ only */
328 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 /* BB Rev 4.2+ only */
331 #define AR_PHY_POWER_TX_RATE3 0xA234
332 #define AR_PHY_POWER_TX_RATE4 0xA238
334 #define AR_PHY_FAST_ADC 0xA24C
335 #define AR_PHY_BLUETOOTH 0xA254
337 #define AR_PHY_TPCRG1 0xA258 /* ar2413 power control */
338 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
340 #define AR_PHY_TPCRG1_PDGAIN_SETTING1 0x00030000
342 #define AR_PHY_TPCRG1_PDGAIN_SETTING2 0x000c0000
344 #define AR_PHY_TPCRG1_PDGAIN_SETTING3 0x00300000
347 #define AR_PHY_TPCRG5 0xA26C /* ar2413 power control */
348 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
349 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
350 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
352 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
354 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
356 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000