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/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x0000000
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/freebsd/usr.sbin/bluetooth/iwmbtfw/
H A Diwmbt_fw.c54 if (fd < 0) { in iwmbt_fw_read()
56 return (0); in iwmbt_fw_read()
59 if (fstat(fd, &sb) != 0) { in iwmbt_fw_read()
62 return (0); in iwmbt_fw_read()
69 return (0); in iwmbt_fw_read()
74 if (r < 0) { in iwmbt_fw_read()
78 return (0); in iwmbt_fw_read()
87 return (0); in iwmbt_fw_read()
92 memset(fw, 0, sizeof(*fw)); in iwmbt_fw_read()
109 memset(fw, 0, sizeo in iwmbt_fw_free()
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/freebsd/sys/contrib/ncsw/Peripherals/FM/Pcd/
H A Dfm_plcr.h49 #define FM_PCD_PLCR_PAR_GO 0x80000000
50 #define FM_PCD_PLCR_PAR_PWSEL_MASK 0x0000FFFF
51 #define FM_PCD_PLCR_PAR_R 0x40000000
57 #define FM_PCD_PLCR_PEMODE_PI 0x80000000
58 #define FM_PCD_PLCR_PEMODE_CBLND 0x40000000
59 #define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000
60 #define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000
61 #define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000
62 #define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000
63 #define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/davinci/
H A Dda850-lcdk.dts24 /* 128 MB DDR2 SDRAM @ 0xc0000000 */
25 reg = <0xc0000000 0x08000000>;
35 reg = <0xc3000000 0x1000000>;
122 #size-cells = <0>;
126 #size-cells = <0>;
128 port@0 {
129 reg = <0>;
205 0x0
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/freebsd/sys/arm/arm/
H A Ddisassem.c76 * m - m register (bits 0-3)
81 * h - 3rd fp operand (register/immediate) (bits 0-4)
83 * t - thumb branch address (bits 24, 0-23)
84 * k - breakpoint comment (bits 0-3, 8-19)
87 * c - comment field bits(0-23)
112 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */
113 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */
114 { 0x0f000000, 0x0f000000, "swi", "c" },
115 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */
116 { 0x0f000000, 0x0a000000, "b", "b" },
[all …]
/freebsd/sys/dev/agp/
H A Dagp_amd64.c84 agp_find_caps(dev) == 0) in agp_amd64_match()
88 case 0x74541022: in agp_amd64_match()
90 case 0x07551039: in agp_amd64_match()
92 case 0x07601039: in agp_amd64_match()
94 case 0x168910b9: in agp_amd64_match()
96 case 0x00d110de: in agp_amd64_match()
97 if (agp_amd64_nvidia_match(0x00d2)) in agp_amd64_match()
100 case 0x00e110de: in agp_amd64_match()
101 if (agp_amd64_nvidia_match(0x00e2)) in agp_amd64_match()
104 case 0x02041106: in agp_amd64_match()
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie_axi_reg.h53 /* [0x0] */
56 /* [0x8] */
58 /* [0xc] */
60 /* [0x10] */
62 /* [0x14] */
64 /* [0x18] */
66 /* [0x1c] */
68 /* [0x20] */
70 /* [0x24] */
72 /* [0x28] */
[all …]
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-fh.h22 #define FH_MEM_LOWER_BOUND (0x1000)
23 #define FH_MEM_UPPER_BOUND (0x2000)
24 #define FH_MEM_LOWER_BOUND_GEN2 (0xa06000)
25 #define FH_MEM_UPPER_BOUND_GEN2 (0xa08000)
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
44 #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
52 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
54 * aligned (address bits 0-7 must be 0).
59 * 27-0
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/freebsd/sys/dev/neta/
H A Dif_mvnetareg.h39 #define MVNETA_SIZE 0x4000
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
61 #define MVNETA_QUEUE_ALL 0xff
67 * GbE0 BASE 0x00007.0000 SIZE 0x4000
68 * GbE1 BASE 0x00007.4000 SIZE 0x4000
73 #define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
74 #define MVNETA_S(n) (0x2204 + ((n) << 3)) /* Size */
75 #define MVNETA_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */
76 #define MVNETA_BARE 0x2290 /* Base Address Enable */
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dnvm_cfg.h43 #define NVM_CFG_version 0x83306
54 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
55 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
64 u32 generic_cont0; /* 0x0 */
65 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
66 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
67 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
68 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
69 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
70 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
[all …]
H A Decore_int.c96 #define ATTENTION_PARITY (1 << 0)
98 #define ATTENTION_LENGTH_MASK (0x00000ff0)
108 #define ATTENTION_OFFSET_MASK (0x000ff000)
111 #define ATTENTION_BB_MASK (0x00700000)
139 0xffffffff); in ecore_mcp_attn_cb()
144 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK (0x3c000)
146 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK (0x03fc0)
148 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK (0x00020)
150 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK (0x0001e)
152 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK (0x1)
[all …]
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/sys/dev/e1000/
H A De1000_defines.h44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/freebsd/sys/dev/igc/
H A Digc_defines.h16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
18 #define IGC_WUC_PME_STATUS 0x00000004 /* PME Status */
19 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
20 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/freebsd/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]
/freebsd/sys/dev/iwm/
H A Dif_iwmreg.h94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
101 #define IWM_CSR_GP_CNTRL (0x024)
104 #define IWM_CSR_INT_PERIODIC_REG (0x005)
111 * 3-2: Revision step: 0
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/freebsd/sys/dev/bce/
H A Dif_bcereg.h82 /* MII Control Register 0x0 */
102 /* MII Status Register 0x1 */
122 /* MII Autoneg Advertisement Register 0x4 */
142 /* MII Autoneg Link Partner Ability Register 0x5 */
162 /* 1000Base-T Control Register 0x09 */
182 /* MII 1000Base-T Status Register 0x0a */
194 /* MII Extended Status Register 0x0f */
214 /* MII Autoneg Link Partner Ability Register 0x19 */
245 #define BCE_CP_LOAD 0x00000001
246 #define BCE_CP_SEND 0x00000002
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32LE-rev1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DUTF-16BE1 0x0100 = 0x00000001
2 0x0101 = 0x00000101
3 0x0102 = 0x00000201
4 0x0103 = 0x00000301
5 0x0104 = 0x00000401
6 0x0105 = 0x00000501
7 0x0106 = 0x00000601
8 0x0107 = 0x00000701
9 0x0108 = 0x00000801
10 0x0109 = 0x00000901
[all …]
H A DUTF-16LE1 0x0100 = 0x00000100
2 0x0101 = 0x00000101
3 0x0102 = 0x00000102
4 0x0103 = 0x00000103
5 0x0104 = 0x00000104
6 0x0105 = 0x00000105
7 0x0106 = 0x00000106
8 0x0107 = 0x00000107
9 0x0108 = 0x00000108
10 0x0109 = 0x00000109
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201F
[all...]