Lines Matching +full:0 +full:x00000ff0
39 #define MVNETA_SIZE 0x4000
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
61 #define MVNETA_QUEUE_ALL 0xff
67 * GbE0 BASE 0x00007.0000 SIZE 0x4000
68 * GbE1 BASE 0x00007.4000 SIZE 0x4000
73 #define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
74 #define MVNETA_S(n) (0x2204 + ((n) << 3)) /* Size */
75 #define MVNETA_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */
76 #define MVNETA_BARE 0x2290 /* Base Address Enable */
77 #define MVNETA_EPAP 0x2294 /* Ethernet Port Access Protect */
80 #define MVNETA_PHYADDR 0x2000
81 #define MVNETA_SMI 0x2004
82 #define MVNETA_EUDA 0x2008 /* Ethernet Unit Default Address */
83 #define MVNETA_EUDID 0x200c /* Ethernet Unit Default ID */
84 #define MVNETA_MBUS_CONF 0x2010 /* MBUS configuration */
85 #define MVNETA_MBUS_RETRY_EN 0x20 /* MBUS transactions retry enable */
86 #define MVNETA_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */
87 #define MVNETA_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */
88 #define MVNETA_EUEA 0x2094 /* Ethernet Unit Error Address */
89 #define MVNETA_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */
90 #define MVNETA_EUC 0x20b0 /* Ethernet Unit Control */
93 #define MVNETA_SDC 0x241c /* SDMA Configuration */
96 #define MVNETA_PACC 0x2500 /* Port Acceleration Mode */
97 #define MVNETA_PV 0x25bc /* Port Version */
100 #define MVNETA_EVLANE 0x2410 /* VLAN EtherType */
101 #define MVNETA_MACAL 0x2414 /* MAC Address Low */
102 #define MVNETA_MACAH 0x2418 /* MAC Address High */
104 #define MVNETA_DSCP(n) (0x2420 + ((n) << 2))
105 #define MVNETA_VPT2P 0x2440 /* VLAN Priority Tag to Priority */
106 #define MVNETA_ETP 0x24bc /* Ethernet Type Priority */
108 #define MVNETA_DFSMT(n) (0x3400 + ((n) << 2))
111 #define MVNETA_DFOMT(n) (0x3500 + ((n) << 2))
114 #define MVNETA_DFUT(n) (0x3600 + ((n) << 2))
118 #define MVNETA_PMFS 0x247c /* Port Rx Minimal Frame Size */
119 #define MVNETA_PDFC 0x2484 /* Port Rx Discard Frame Counter */
120 #define MVNETA_POFC 0x2488 /* Port Overrun Frame Counter */
121 #define MVNETA_RQC 0x2680 /* Receive Queue Command */
124 #define MVNETA_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/
125 #define MVNETA_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */
126 #define MVNETA_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/
127 #define MVNETA_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/
128 #define MVNETA_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/
129 #define MVNETA_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */
130 #define MVNETA_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/
131 #define MVNETA_PRXDI(q) (0x1520 + ((q) << 2)) /*P RXqueues Stat Update*/
132 #define MVNETA_PRXINIT 0x1cc0 /* Port RX Initialization */
134 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */
137 #define MVNETA_TQC 0x2448 /* Transmit Queue Command */
138 #define MVNETA_TQC_1 0x24e4
139 #define MVNETA_PXTFTT 0x2478 /* Port Tx FIFO Threshold */
140 #define MVNETA_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/
141 #define MVNETA_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */
144 #define MVNETA_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/
145 #define MVNETA_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/
146 #define MVNETA_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/
147 #define MVNETA_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/
148 #define MVNETA_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/
149 #define MVNETA_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/
150 #define MVNETA_PTXINIT 0x3cf0 /* Port TX Initialization */
154 #define MVNETA_TXMH(n) (0x3d44 + ((n) << 2))
155 #define MVNETA_TXMTU 0x3d88
158 #define MVNETA_TQFPC_V1 0x24dc /* Transmit Queue Fixed Priority Cfg */
159 #define MVNETA_TQTBC_V1 0x24e0 /* Transmit Queue Token-Bucket Cfg */
160 #define MVNETA_MTU_V1 0x24e8 /* MTU */
161 #define MVNETA_PMTBS_V1 0x24ec /* Port Max Token-Bucket Size */
162 #define MVNETA_TQTBCOUNT_V1(q) (0x2700 + ((q) << 4))
164 #define MVNETA_TQTBCONFIG_V1(q) (0x2704 + ((q) << 4))
166 #define MVNETA_PTTBC_V1 0x2740 /* Port Transmit Backet Counter */
169 #define MVNETA_TQC1_V3 0x3e00 /* Transmit Queue Command1 */
170 #define MVNETA_TQFPC_V3 0x3e04 /* Transmit Queue Fixed Priority Cfg */
171 #define MVNETA_BRC_V3 0x3e08 /* Basic Refill No of Clocks */
172 #define MVNETA_MTU_V3 0x3e0c /* MTU */
173 #define MVNETA_PREFILL_V3 0x3e10 /* Port Backet Refill */
174 #define MVNETA_PMTBS_V3 0x3e14 /* Port Max Token-Bucket Size */
175 #define MVNETA_QREFILL_V3(q) (0x3e20 + ((q) << 2))
177 #define MVNETA_QMTBS_V3(q) (0x3e40 + ((q) << 2))
179 #define MVNETA_QTTBC_V3(q) (0x3e60 + ((q) << 2))
181 #define MVNETA_TQAC_V3(q) (0x3e80 + ((q) << 2))
183 #define MVNETA_TQIPG_V3(q) (0x3ea0 + ((q) << 2))
185 #define MVNETA_HITKNINLOPKT_V3 0x3eb0 /* High Token in Low Packet */
186 #define MVNETA_HITKNINASYNCPKT_V3 0x3eb4 /* High Token in Async Packet */
187 #define MVNETA_LOTKNINASYNCPKT_V3 0x3eb8 /* Low Token in Async Packet */
188 #define MVNETA_TS_V3 0x3ebc /* Token Speed */
191 #define MVNETA_PXC 0x2400 /* Port Configuration */
192 #define MVNETA_PXCX 0x2404 /* Port Configuration Extend */
193 #define MVNETA_MH 0x2454 /* Marvell Header */
196 #define MVNETA_PSC0 0x243c /* Port Serial Control0 */
197 #define MVNETA_PS0 0x2444 /* Ethernet Port Status */
198 #define MVNETA_PSERDESCFG 0x24a0 /* Serdes Configuration */
199 #define MVNETA_PSERDESSTS 0x24a4 /* Serdes Status */
200 #define MVNETA_PSOMSCD 0x24f4 /* One mS Clock Divider */
201 #define MVNETA_PSPFCCD 0x24f8 /* Periodic Flow Control Clock Divider*/
204 #define MVNETA_PSPC 0x2c14 /* Port Serial Parameters Config */
205 #define MVNETA_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */
208 #define MVNETA_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/
211 #define MVNETA_PMACC0 0x2c00 /* Port MAC Control 0 */
212 #define MVNETA_PMACC1 0x2c04 /* Port MAC Control 1 */
213 #define MVNETA_PMACC2 0x2c08 /* Port MAC Control 2 */
214 #define MVNETA_PMACC3 0x2c48 /* Port MAC Control 3 */
215 #define MVNETA_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/
216 #define MVNETA_PMACC4 0x2c90 /* Port MAC Control 4 */
219 #define MVNETA_PIC 0x2c20
220 #define MVNETA_PIM 0x2c24
223 #define MVNETA_LPIC0 0x2cc0 /* LowPowerIdle control 0 */
224 #define MVNETA_LPIC1 0x2cc4 /* LPI control 1 */
225 #define MVNETA_LPIC2 0x2cc8 /* LPI control 2 */
226 #define MVNETA_LPIS 0x2ccc /* LPI status */
227 #define MVNETA_LPIC 0x2cd0 /* LPI counter */
230 #define MVNETA_PPRBSS 0x2c38 /* Port PRBS Status */
231 #define MVNETA_PPRBSEC 0x2c3c /* Port PRBS Error Counter */
234 #define MVNETA_PSR 0x2c10 /* Port Status Register0 */
237 #define MVNETA_PCP2Q(cpu) (0x2540 + ((cpu) << 2))
238 #define MVNETA_PRXITTH(q) (0x2580 + ((q) << 2))
240 #define MVNETA_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/
241 #define MVNETA_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */
242 #define MVNETA_PRXTXIC 0x25a8 /* Port RX_TX Interrupt Cause */
243 #define MVNETA_PRXTXIM 0x25ac /* Port RX_TX Interrupt Mask */
244 #define MVNETA_PMIC 0x25b0 /* Port Misc Interrupt Cause */
245 #define MVNETA_PMIM 0x25b4 /* Port Misc Interrupt Mask */
246 #define MVNETA_PIE 0x25b8 /* Port Interrupt Enable */
247 #define MVNETA_PSNPCFG 0x25e4 /* Port Snoop Config */
248 #define MVNETA_PSNPCFG_DESCSNP_MASK (0x3 << 4)
249 #define MVNETA_PSNPCFG_BUFSNP_MASK (0x3 << 8)
252 #define MVNETA_PEUIAE 0x2494 /* Port Internal Address Error */
255 #define MVNETA_PPLLC 0x2e04 /* Power and PLL Control */
256 #define MVNETA_TESTC0 0x2e54 /* PHY Test Control 0 */
257 #define MVNETA_TESTPRBSEC0 0x2e7c /* PHY Test PRBS Error Counter 0 */
258 #define MVNETA_TESTPRBSEC1 0x2e80 /* PHY Test PRBS Error Counter 1 */
259 #define MVNETA_TESTOOB0 0x2e84 /* PHY Test OOB 0 */
260 #define MVNETA_DLE 0x2e8c /* Digital Loopback Enable */
261 #define MVNETA_RCS 0x2f18 /* Reference Clock Select */
262 #define MVNETA_COMPHYC 0x2f18 /* COMPHY Control */
266 * GbE0 BASE 0x00007.3000
267 * GbE1 BASE 0x00007.7000
269 /* MAC MIB Counters 0x3000 - 0x307c */
270 #define MVNETA_PORTMIB_BASE 0x3000
271 #define MVNETA_PORTMIB_SIZE 0x0080
275 #define MVNETA_MIB_RX_GOOD_OCT 0x00 /* 64bit */
276 #define MVNETA_MIB_RX_BAD_OCT 0x08
277 #define MVNETA_MIB_RX_GOOD_FRAME 0x10
278 #define MVNETA_MIB_RX_BAD_FRAME 0x14
279 #define MVNETA_MIB_RX_BCAST_FRAME 0x18
280 #define MVNETA_MIB_RX_MCAST_FRAME 0x1c
281 #define MVNETA_MIB_RX_FRAME64_OCT 0x20
282 #define MVNETA_MIB_RX_FRAME127_OCT 0x24
283 #define MVNETA_MIB_RX_FRAME255_OCT 0x28
284 #define MVNETA_MIB_RX_FRAME511_OCT 0x2c
285 #define MVNETA_MIB_RX_FRAME1023_OCT 0x30
286 #define MVNETA_MIB_RX_FRAMEMAX_OCT 0x34
289 #define MVNETA_MIB_TX_MAC_TRNS_ERR 0x0c
290 #define MVNETA_MIB_TX_GOOD_OCT 0x38 /* 64bit */
291 #define MVNETA_MIB_TX_GOOD_FRAME 0x40
292 #define MVNETA_MIB_TX_EXCES_COL 0x44
293 #define MVNETA_MIB_TX_MCAST_FRAME 0x48
294 #define MVNETA_MIB_TX_BCAST_FRAME 0x4c
295 #define MVNETA_MIB_TX_MAC_CTL_ERR 0x50
298 #define MVNETA_MIB_FC_SENT 0x54
299 #define MVNETA_MIB_FC_GOOD 0x58
300 #define MVNETA_MIB_FC_BAD 0x5c
303 #define MVNETA_MIB_PKT_UNDERSIZE 0x60
304 #define MVNETA_MIB_PKT_FRAGMENT 0x64
305 #define MVNETA_MIB_PKT_OVERSIZE 0x68
306 #define MVNETA_MIB_PKT_JABBER 0x6c
309 #define MVNETA_MIB_MAC_RX_ERR 0x70
310 #define MVNETA_MIB_MAC_CRC_ERR 0x74
311 #define MVNETA_MIB_MAC_COL 0x78
312 #define MVNETA_MIB_MAC_LATE_COL 0x7c
325 #define MVNETA_BASEADDR_TARGET(target) ((target) & 0xf)
326 #define MVNETA_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8)
327 #define MVNETA_BASEADDR_BASE(base) ((base) & 0xffff0000)
330 #define MVNETA_S_SIZE(size) (((size) - 1) & 0xffff0000)
337 #define MVNETA_EPAP_AC_NAC 0x0 /* No access allowed */
338 #define MVNETA_EPAP_AC_RO 0x1 /* Read Only */
339 #define MVNETA_EPAP_AC_FA 0x3 /* Full access (r/w) */
346 #define MVNETA_PHYADDR_PHYAD(phy) ((phy) & 0x1f)
347 #define MVNETA_PHYADDR_GET_PHYAD(reg) ((reg) & 0x1f)
350 #define MVNETA_SMI_DATA_MASK 0x0000ffff
351 #define MVNETA_SMI_PHYAD(phy) (((phy) & 0x1f) << 16)
352 #define MVNETA_SMI_REGAD(reg) (((reg) & 0x1f) << 21)
353 #define MVNETA_SMI_OPCODE_WRITE (0 << 26)
359 #define MVNETA_EUDID_DIDR_MASK 0x0000000f
360 #define MVNETA_EUDID_DIDR(id) ((id) & 0x0f)
361 #define MVNETA_EUDID_DATTR_MASK 0x00000ff0
362 #define MVNETA_EUDID_DATTR(attr) (((attr) & 0xff) << 4)
365 #define MVNETA_EUIC_ETHERINTSUM (1 << 0)
376 #define MVNETA_EUIAE_INTADDR_MASK 0x000001ff
377 #define MVNETA_EUIAE_INTADDR(addr) ((addr) & 0x1ff)
378 #define MVNETA_EUIAE_GET_INTADDR(addr) ((addr) & 0x1ff)
391 #define MVNETA_SDC_RXBSZ_1_64BITWORDS MVNETA_SDC_RXBSZ(0)
401 #define MVNETA_SDC_TXBSZ_1_64BITWORDS MVNETA_SDC_TXBSZ(0)
411 #define MVNETA_PACC_ACCELERATIONMODE_MASK 0x7
412 #define MVNETA_PACC_ACCELERATIONMODE_EDM 0x1 /* Enhanced Desc Mode */
415 #define MVNETA_PV_VERSION_MASK 0xff
416 #define MVNETA_PV_VERSION(v) ((v) & 0xff)
417 #define MVNETA_PV_GET_VERSION(reg) ((reg) & 0xff)
423 #define MVNETA_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */
425 #define MVNETA_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/
426 #define MVNETA_ETP_ETHERTYPEPRIVAL (0xffff << 5) /*EtherType Prio Value*/
431 #define MVNETA_DF_PASS (1 << 0)
440 #define MVNETA_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c)
443 #define MVNETA_RQC_EN_MASK (0xff << 0) /* Enable Q */
444 #define MVNETA_RQC_ENQ(q) (1 << (0 + (q)))
445 #define MVNETA_RQC_EN(n) ((n) << 0)
446 #define MVNETA_RQC_DIS_MASK (0xff << 8) /* Disable Q */
454 #define MVNETA_PRXC_PACKETOFFSET(o) (((o) & 0xf) << 8)
457 #define MVNETA_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0)
458 #define MVNETA_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16)
461 #define MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x3fff) << 0)
462 #define MVNETA_PRXDQS_BUFFERSIZE(s) (((s) & 0x1fff) << 19)
466 #define MVNETA_PRXDQTH_ODT(x) (((x) & 0x3fff) << 0)
468 #define MVNETA_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16)
472 #define MVNETA_PRXS_ODC(x) (((x) & 0x3fff) << 0)
474 #define MVNETA_PRXS_NODC(x) (((x) & 0x3fff) << 16)
475 #define MVNETA_PRXS_GET_ODC(reg) (((reg) >> 0) & 0x3fff)
476 #define MVNETA_PRXS_GET_NODC(reg) (((reg) >> 16) & 0x3fff)
479 #define MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(x) (((x) & 0xff) << 0)
480 #define MVNETA_PRXSU_NOOFNEWDESCRIPTORS(x) (((x) & 0xff) << 16)
483 #define MVNETA_PRXINIT_RXDMAINIT (1 << 0)
489 #define MVNETA_TQC_EN_MASK (0xff << 0)
490 #define MVNETA_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */
491 #define MVNETA_TQC_EN(n) ((n) << 0)
492 #define MVNETA_TQC_DIS_MASK (0xff << 8)
501 #define MVNETA_PTXDQS_DQS_MASK (0x3fff << 0)
502 #define MVNETA_PTXDQS_DQS(x) (((x) & 0x3fff) << 0)
504 #define MVNETA_PTXDQS_TBT_MASK (0x3fff << 16)
505 #define MVNETA_PTXDQS_TBT(x) (((x) & 0x3fff) << 16)
509 #define MVNETA_PTXS_TBC(x) (((x) & 0x3fff) << 16)
511 #define MVNETA_PTXS_GET_TBC(reg) (((reg) >> 16) & 0x3fff)
513 #define MVNETA_PTXS_PDC(x) ((x) & 0x3fff)
514 #define MVNETA_PTXS_GET_PDC(x) ((x) & 0x3fff)
518 #define MVNETA_PTXSU_NOWD(x) (((x) & 0xff) << 0)
520 #define MVNETA_PTXSU_NORB(x) (((x) & 0xff) << 16)
524 #define MVNETA_TXTBC_TBC(x) (((x) & 0x3fff) << 16)
527 #define MVNETA_PTXINIT_TXDMAINIT (1 << 0)
539 #define MVNETA_PXC_UPM (1 << 0) /* Uni Promisc mode */
564 #define MVNETA_MH_MHEN (1 << 0)
565 #define MVNETA_MH_DAPREFIX (0x3 << 1)
566 #define MVNETA_MH_SPID (0xf << 4)
567 #define MVNETA_MH_MHMASK (0x3 << 8)
568 #define MVNETA_MH_MHMASK_8QUEUES (0x0 << 8)
569 #define MVNETA_MH_MHMASK_4QUEUES (0x1 << 8)
570 #define MVNETA_MH_MHMASK_2QUEUES (0x3 << 8)
571 #define MVNETA_MH_DSAEN_MASK (0x3 << 10)
572 #define MVNETA_MH_DSAEN_DISABLE (0x0 << 10)
573 #define MVNETA_MH_DSAEN_NONEXTENDED (0x1 << 10)
574 #define MVNETA_MH_DSAEN_EXTENDED (0x2 << 10)
580 #define MVNETA_PSERDESCFG_QSGMII (0x0667)
581 #define MVNETA_PSERDESCFG_SGMII (0x0cc7)
583 #define MVNETA_PSC0_FORCE_FC_MASK (0x3 << 5)
584 #define MVNETA_PSC0_FORCE_FC(fc) (((fc) & 0x3) << 5)
585 #define MVNETA_PSC0_FORCE_FC_PAUSE MVNETA_PSC0_FORCE_FC(0x1)
586 #define MVNETA_PSC0_FORCE_FC_NO_PAUSE MVNETA_PSC0_FORCE_FC(0x0)
587 #define MVNETA_PSC0_FORCE_BP_MASK (0x3 << 7)
588 #define MVNETA_PSC0_FORCE_BP(fc) (((fc) & 0x3) << 5)
589 #define MVNETA_PSC0_FORCE_BP_JAM MVNETA_PSC0_FORCE_BP(0x1)
590 #define MVNETA_PSC0_FORCE_BP_NO_JAM MVNETA_PSC0_FORCE_BP(0x0)
597 #define MVNETA_PS0_TXINPROG (1 << 0)
604 #define MVNETA_PSPC_MUST_SET (1 << 3 | 1 << 4 | 1 << 5 | 0x23 << 6)
605 #define MVNETA_PSP1C_MUST_SET (1 << 0 | 1 << 1 | 1 << 2)
611 #define MVNETA_PANC_FORCELINKFAIL (1 << 0)
629 /* Port MAC Control 0 (MVNETA_PMACC0) */
630 #define MVNETA_PMACC0_PORTEN (1 << 0)
632 #define MVNETA_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) << 2) & 0x7ffc)
633 #define MVNETA_PMACC0_FRAMESIZELIMIT_MASK (0x7ffc)
640 #define MVNETA_PMACC2_INBANDANMODE (1 << 0)
649 #define MVNETA_PMACC2_SDTT_RM (0 << 12) /* Regular Mode */
656 #define MVNETA_PMACC3_IPG_MASK 0x7f80
662 #define MVNETA_PI_INTSUM (1 << 0)
678 /* LPI Control 0 (MVNETA_LPIC0) */
679 #define MVNETA_LPIC0_LILIMIT(x) (((x) & 0xff) << 0)
680 #define MVNETA_LPIC0_TSLIMIT(x) (((x) & 0xff) << 8)
683 #define MVNETA_LPIC1_LPIRE (1 << 0) /* LPI request enable */
686 #define MVNETA_LPIC1_TWLIMIT(x) (((x) & 0xfff) << 4)
689 #define MVNETA_LPIC2_MUSTSET 0x17d
692 #define MVNETA_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */
702 #define MVNETA_PPRBSS_PRBSCHECKLOCKED (1 << 0)
709 #define MVNETA_PSR_LINKUP (1 << 0)
729 #define MVNETA_PCP2Q_TXQEN_MASK (0xff << 8)
730 #define MVNETA_PCP2Q_RXQEN(q) (1 << ((q) + 0))
731 #define MVNETA_PCP2Q_RXQEN_MASK (0xff << 0)
734 #define MVNETA_PRXITTH_RITT(t) ((t) & 0xffffff)
737 #define MVNETA_PRXTXTI_TBTCQ(q) (1 << ((q) + 0))
738 #define MVNETA_PRXTXTI_TBTCQ_MASK (0xff << 0)
739 #define MVNETA_PRXTXTI_GET_TBTCQ(reg) (((reg) >> 0) & 0xff)
742 #define MVNETA_PRXTXTI_RBICTAPQ_MASK (0xff << 8)
743 #define MVNETA_PRXTXTI_GET_RBICTAPQ(reg) (((reg) >> 8) & 0xff)
746 #define MVNETA_PRXTXTI_RDTAQ_MASK (0xff << 16)
747 #define MVNETA_PRXTXTI_GET_RDTAQ(reg) (((reg) >> 16) & 0xff)
754 #define MVNETA_PRXTXI_TBRQ(q) (1 << ((q) + 0))
755 #define MVNETA_PRXTXI_TBRQ_MASK (0xff << 0)
756 #define MVNETA_PRXTXI_GET_TBRQ(reg) (((reg) >> 0) & 0xff)
758 #define MVNETA_PRXTXI_RPQ_MASK (0xff << 8)
759 #define MVNETA_PRXTXI_GET_RPQ(reg) (((reg) >> 8) & 0xff)
761 #define MVNETA_PRXTXI_RREQ_MASK (0xff << 16)
762 #define MVNETA_PRXTXI_GET_RREQ(reg) (((reg) >> 16) & 0xff)
768 #define MVNETA_PMI_PHYSTATUSCHNG (1 << 0)
779 #define MVNETA_PMI_TREQ_MASK (0xff << 24) /* TxResourceErrorQ */
782 #define MVNETA_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0))
784 #define MVNETA_PIE_RXPKTINTRPTENB_MASK (0xff << 0)
785 #define MVNETA_PIE_TXPKTINTRPTENB_MASK (0xff << 8)
790 #define MVNETA_PEUIAE_ADDR_MASK (0x3fff)
791 #define MVNETA_PEUIAE_ADDR(addr) ((addr) & 0x3fff)
792 #define MVNETA_PEUIAE_GET_ADDR(reg) ((reg) & 0x3fff)
798 #define MVNETA_PPLLC_REF_FREF_SEL_MASK (0xf << 0)
800 #define MVNETA_PPLLC_PHY_MODE_SATA (0 << 5)
811 #define MVNETA_DLE_LOCAL_SEL_BITS_10BITS (0 << 10)
827 uint32_t command; /* off 0x00: commands */
829 uint16_t bytecnt; /* 0ff 0x04: buffer byte count */
830 uint32_t bufptr_pa; /* off 0x08: buffer ptr(PA) */
831 uint32_t flags; /* off 0x0c: flags */
832 uint32_t reserved0; /* off 0x10 */
833 uint32_t reserved1; /* off 0x14 */
834 uint32_t reserved2; /* off 0x18 */
835 uint32_t reserved3; /* off 0x1c */
864 #define MVNETA_RX_L3_IP (1 << 24) /* IP Type 0:IP6 1:IP4 */
867 #define MVNETA_RX_L4_TCP (0x00 << 21)
868 #define MVNETA_RX_L4_UDP (0x01 << 21)
869 #define MVNETA_RX_L4_OTH (0x10 << 21)
873 #define MVNETA_RX_EC_CE (0x00 << 17) /* CRC error */
874 #define MVNETA_RX_EC_OR (0x01 << 17) /* FIFO overrun */
875 #define MVNETA_RX_EC_MF (0x10 << 17) /* Max. frame len */
876 #define MVNETA_RX_EC_RE (0x11 << 17) /* Resource error */
878 /* bit 15:0 reserved */
884 #define MVNETA_TX_CMD_L4_CHECKSUM_MASK (0x3 << 30) /* Do L4 Checksum */
885 #define MVNETA_TX_CMD_L4_CHECKSUM_FRAG (0x0 << 30)
886 #define MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG (0x1 << 30)
887 #define MVNETA_TX_CMD_L4_CHECKSUM_NONE (0x2 << 30)
888 #define MVNETA_TX_CMD_PACKET_OFFSET_MASK (0x7f << 23) /* Payload offset */
889 #define MVNETA_TX_CMD_W_PACKET_OFFSET(v) (((v) & 0x7f) << 23)
895 #define MVNETA_TX_CMD_L3_IP4 (0 << 17)
897 #define MVNETA_TX_CMD_L4_TCP (0 << 16)
900 #define MVNETA_TX_CMD_IP_HEADER_LEN_MASK (0x1f << 8) /* IP header len >> 2 */
901 #define MVNETA_TX_CMD_IP_HEADER_LEN(v) (((v) & 0x1f) << 8)
903 #define MVNETA_TX_CMD_L3_OFFSET_MASK (0x7f << 0) /* offset of L3 hdr. */
904 #define MVNETA_TX_CMD_L3_OFFSET(v) (((v) & 0x7f) << 0)
912 #define MVNETA_TX_F_MH_SEL (0xf << 4) /* Marvell Header */
915 #define MVNETA_TX_F_EC_LC (0x00 << 1) /* Late Collision */
916 #define MVNETA_TX_F_EC_UR (0x01 << 1) /* Underrun */
917 #define MVNETA_TX_F_EC_RL (0x10 << 1) /* Excess. Collision */
918 #define MVNETA_TX_F_EC_RESERVED (0x11 << 1)
919 #define MVNETA_TX_F_ES (1 << 0) /* Error summary */
921 #define MVNETA_ERROR_SUMMARY (1 << 0)
923 #define MVNETA_BUFFER_OWNED_BY_HOST (0UL << 31)