Home
last modified time | relevance | path

Searched +full:0 +full:x000001ff (Results 1 – 25 of 55) sorted by relevance

123

/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x0000000
[all...]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852b_table.c10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x4451147
[all...]
H A Drtw8852b.c22 {5, 341, grp_0}, /* ACH 0 */
26 {0, 0, grp_0}, /* ACH 4 */
27 {0, 0, grp_0}, /* ACH 5 */
28 {0, 0, grp_0}, /* ACH 6 */
29 {0, 0, grp_0}, /* ACH 7 */
32 {0,
[all...]
/freebsd/sys/dev/isci/scil/
H A Dsati_write_buffer.c66 #define WRITE_BUFFER_WRITE_DATA 0x02
67 #define WRITE_BUFFER_DOWNLOAD_SAVE 0x05
68 #define WRITE_BUFFER_OFFSET_DOWNLOAD_SAVE 0x07
110 (buffer_offset == 0) && in sati_write_buffer_translate_command()
111 (sati_get_cdb_byte(cdb, 2) == 0)) in sati_write_buffer_translate_command()
150 if(((allocation_length & 0x000001FF) == 0) && //Bits 08:00 need to be zero per SAT2v7 in sati_write_buffer_translate_command()
151 ((buffer_offset & 0x000001FF) == 0) && in sati_write_buffer_translate_command()
154 (allocation_length == 0))) in sati_write_buffer_translate_command()
/freebsd/sys/net80211/
H A Dieee80211_radiotap.h70 uint8_t it_version; /* Version 0. Only increases
83 * (0x80000000) to extend the
111 * Tx/Rx data rate. If bit 0x80 is set then it represents an
146 * power set at factory calibration. 0 is max power.
152 * set at factory calibration. 0 is max power. Monotonically
170 * The first antenna is antenna 0.
208 IEEE80211_RADIOTAP_TSFT = 0,
247 #define IEEE80211_CHAN_TURBO 0x00000010 /* Turbo channel */
248 #define IEEE80211_CHAN_CCK 0x00000020 /* CCK channel */
249 #define IEEE80211_CHAN_OFDM 0x0000004
[all...]
/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x020000
[all...]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drx.h14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
27 * (REPLY_RX_PHY_CMD = 0xc0)
70 * bits 0:3 - reserved
78 CSUM_RXA_RESERVED_MASK = 0x000f,
79 CSUM_RXA_MICSIZE_MASK = 0x00f0,
80 CSUM_RXA_HEADERLEN_MASK = 0x1f00,
110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
114 RX_RES_PHY_FLAGS_ANTENNA = (0x
[all...]
/freebsd/sys/contrib/dev/mediatek/mt76/mt76x2/
H A Dinit.c86 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
88 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
92 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
94 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
98 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
101 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
104 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \ in mt76_write_mac_initvals()
107 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f)) in mt76_write_mac_initvals()
111 { MT_PBF_SYS_CTRL, 0x00080c00 }, in mt76_write_mac_initvals()
112 { MT_PBF_CFG, 0x1efebcff }, in mt76_write_mac_initvals()
[all …]
/freebsd/sys/dev/gem/
H A Dif_gemreg.h37 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
38 #define GEM_CONFIG 0x0004 /* config reg */
39 #define GEM_STATUS 0x000c /* status reg */
40 /* Note: Reading the status reg clears bits 0-6. */
41 #define GEM_INTMASK 0x0010
42 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
43 #define GEM_STATUS_ALIAS 0x001c
46 #define GEM_SEB_ARB 0x00000002 /* Arbitration status */
47 #define GEM_SEB_RXWON 0x00000004
50 #define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */
[all …]
/freebsd/sys/dev/irdma/
H A Dirdma_cm.h49 #define IETF_MPA_V2_FLAG 0x10
50 #define SNDMARKER_SEQNMASK 0x000001ff
54 #define IETF_PEER_TO_PEER 0x8000
55 #define IETF_FLPDU_ZERO_LEN 0x4000
56 #define IETF_RDMA0_WRITE 0x8000
57 #define IETF_RDMA0_READ 0x4000
58 #define IETF_NO_IRD_ORD 0x3fff
62 #define IRDMA_PASSIVE_STATE_INDICATED 0
77 #define IRDMA_DEFAULT_TTL 0x40
79 #define IRDMA_DEFAULT_SS_THRESH 0x3fffffff
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
[all …]
/freebsd/sys/dev/sound/pci/
H A Demuxkireg.h50 #define EMU_PTR 0x00
51 #define EMU_PTR_CHNO_MASK 0x0000003f
52 #define EMU_PTR_ADDR_MASK 0x07ff0000
53 #define EMU_A_PTR_ADDR_MASK 0x0fff0000
55 #define EMU_DATA 0x04
57 #define EMU_IPR 0x08
58 #define EMU_IPR_RATETRCHANGE 0x01000000
59 #define EMU_IPR_FXDSP 0x00800000
60 #define EMU_IPR_FORCEINT 0x00400000
61 #define EMU_PCIERROR 0x00200000
[all …]
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_tgec.h41 #define TGEC_TX_IPG_LENGTH_MASK 0x000003ff
73 #define CMD_CFG_EN_TIMESTAMP 0x00100000
74 #define CMD_CFG_TX_ADDR_INS_SEL 0x00080000
75 #define CMD_CFG_NO_LEN_CHK 0x00020000
76 #define CMD_CFG_SEND_IDLE 0x00010000
77 #define CMD_CFG_RX_ER_DISC 0x00004000
78 #define CMD_CFG_CMD_FRM_EN 0x00002000
79 #define CMD_CFG_STAT_CLR 0x00001000
80 #define CMD_CFG_LOOPBACK_EN 0x00000400
81 #define CMD_CFG_TX_ADDR_INS 0x00000200
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_ec_regs.h60 /* [0x0] Ethernet controller Version */
62 /* [0x4] Enable modules operation. */
64 /* [0x8] Enable FIFO operation on the EC side. */
66 /* [0xc] General L2 configuration for the Ethernet controlle ... */
68 /* [0x10] Configure protocol index values */
70 /* [0x14] Configure protocol index values (extended protocols ... */
72 /* [0x18] Enable modules operation (extended operations). */
77 /* [0x0] General configuration of the MAC side of the Ethern ... */
79 /* [0x4] Minimum packet size */
81 /* [0x8] Maximum packet size */
[all …]
/freebsd/sys/dev/ral/
H A Drt2560reg.h19 #define RT2560_DEFAULT_RSSI_CORR 0x79
36 #define RT2560_CSR0 0x0000 /* ASIC version number */
37 #define RT2560_CSR1 0x0004 /* System control */
38 #define RT2560_CSR3 0x000c /* STA MAC address 0 */
39 #define RT2560_CSR4 0x0010 /* STA MAC address 1 */
40 #define RT2560_CSR5 0x0014 /* BSSID 0 */
41 #define RT2560_CSR6 0x0018 /* BSSID 1 */
42 #define RT2560_CSR7 0x001c /* Interrupt source */
43 #define RT2560_CSR8 0x0020 /* Interrupt mask */
44 #define RT2560_CSR9 0x0024 /* Maximum frame length */
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300desc.h94 #define AR_desc_len 0x000000ff
95 #define AR_rx_priority 0x00000100
96 #define AR_tx_qcu_num 0x00000f00
98 #define AR_ctrl_stat 0x00004000
100 #define AR_tx_rx_desc 0x00008000
102 #define AR_desc_id 0xffff0000
113 #define AR_buf_len 0x0fff0000
117 #define AR_tx_desc_id 0xffff0000
119 #define AR_tx_ptr_chk_sum 0x0000ffff
122 #define AR_frame_len 0x00000fff
[all …]
/freebsd/sys/contrib/dev/acpica/include/
H A Dacoutput.h163 #define ACPI_UTILITIES 0x00000001
164 #define ACPI_HARDWARE 0x00000002
165 #define ACPI_EVENTS 0x00000004
166 #define ACPI_TABLES 0x00000008
167 #define ACPI_NAMESPACE 0x00000010
168 #define ACPI_PARSER 0x00000020
169 #define ACPI_DISPATCHER 0x00000040
170 #define ACPI_EXECUTER 0x00000080
171 #define ACPI_RESOURCES 0x00000100
172 #define ACPI_CA_DEBUGGER 0x00000200
[all …]
/freebsd/sys/dev/cas/
H A Dif_casreg.h42 #define CAS_CAW 0x0004 /* core arbitration weight */
43 #define CAS_INF_BURST 0x0008 /* infinite burst enable */
44 #define CAS_STATUS 0x000c /* interrupt status */
45 #define CAS_INTMASK 0x0010 /* interrupt mask */
46 #define CAS_CLEAR_ALIAS 0x0014 /* clear mask alias */
47 #define CAS_STATUS_ALIAS 0x001c /* interrupt status alias */
48 #define CAS_ERROR_STATUS 0x1000 /* PCI error status */
49 #define CAS_ERROR_MASK 0x1004 /* PCI error mask */
50 #define CAS_BIM_CONF 0x1008 /* BIM configuration */
51 #define CAS_BIM_DIAG 0x100c /* BIM diagnostic */
[all …]
/freebsd/sys/contrib/ncsw/Peripherals/FM/MACSEC/
H A Dfm_macsec_master.h56 #define FM_MACSEC_EX_TX_SC_0 0x80000000
58 #define FM_MACSEC_EX_ECC 0x00000001
65 default: bitMask = 0;break;}
67 #define FM_MACSEC_USER_EX_SINGLE_BIT_ECC 0x80000000
68 #define FM_MACSEC_USER_EX_MULTI_BIT_ECC 0x40000000
75 default: bitMask = 0;break;}
81 #define FM_MACSEC_EV_TX_SC_0_NEXT_PN 0x80000000
87 default: bitMask = 0;break;}
95 #define DEFAULT_exceptions (FM_MACSEC_EX_TX_SC(0) |\
113 #define DEFAULT_events (FM_MACSEC_EV_TX_SC_NEXT_PN(0) |\
[all …]
/freebsd/sys/netinet6/
H A Din6.h141 #define IN6MASK0 {{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}}
142 #define IN6MASK32 {{{ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, \
143 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }}}
144 #define IN6MASK64 {{{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }}}
146 #define IN6MASK96 {{{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
147 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }}}
148 #define IN6MASK128 {{{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
149 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }}}
169 #define IPV6_ADDR_INT32_MNL 0xff010000
[all …]
/freebsd/sys/dev/mvs/
H A Dmvs.h32 #define CHIP_PCIEIC 0x1900 /* PCIe Interrupt Cause */
33 #define CHIP_PCIEIM 0x1910 /* PCIe Interrupt Mask */
34 #define CHIP_PCIIC 0x1d58 /* PCI Interrupt Cause */
35 #define CHIP_PCIIM 0x1d5c /* PCI Interrupt Mask */
36 #define CHIP_MIC 0x1d60 /* Main Interrupt Cause */
37 #define CHIP_MIM 0x1d64 /* Main Interrupt Mask */
38 #define CHIP_SOC_MIC 0x20 /* SoC Main Interrupt Cause */
39 #define CHIP_SOC_MIM 0x24 /* SoC Main Interrupt Mask */
40 #define IC_ERR_IRQ (1 << 0) /* shift by (2 * port #) */
42 #define IC_HC0 0x000001ff /* bits 0-8 = HC0 */
[all …]

123