Lines Matching +full:0 +full:x000001ff
22 {5, 341, grp_0}, /* ACH 0 */
26 {0, 0, grp_0}, /* ACH 4 */
27 {0, 0, grp_0}, /* ACH 5 */
28 {0, 0, grp_0}, /* ACH 6 */
29 {0, 0, grp_0}, /* ACH 7 */
32 {0, 0, grp_0}, /* B1MGQ */
33 {0, 0, grp_0}, /* B1HIQ */
34 {40, 0, 0} /* FWCMDQ */
38 446, /* Group 0 */
39 0, /* Group 1 */
41 0 /* WP threshold */
106 .mpdu_tx_imr_set = 0,
107 .mpdu_rx_imr_set = 0,
124 .other_disp_imr_set = 0,
127 .bbrpt_err_imr_set = 0,
134 .cdma_imr_1_reg = 0,
135 .cdma_imr_1_clr = 0,
136 .cdma_imr_1_set = 0,
138 .phy_intf_imr_clr = 0,
139 .phy_intf_imr_set = 0,
149 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
156 0xf},
159 0x0},
201 {255, 0, 0, 7}, /* 0 -> original */
202 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
203 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
204 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
205 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
206 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
207 {6, 1, 0, 7},
208 {13, 1, 0, 7},
209 {13, 1, 0, 7}
213 {255, 0, 0, 7}, /* 0 -> original */
214 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
215 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
216 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
217 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
218 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
219 {255, 1, 0, 7},
220 {255, 1, 0, 7},
221 {255, 1, 0, 7}
225 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
226 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
227 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
228 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
229 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
230 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
231 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
232 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
233 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
234 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
235 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
236 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
237 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
238 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738),
239 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688),
240 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694),
250 if (efuse->rfe_type == 0x5)
279 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1);
280 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3);
318 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
329 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
332 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
335 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
338 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
354 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9);
355 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA);
359 rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA);
380 return 0;
394 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
397 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
400 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
403 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
422 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
428 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
441 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3);
444 return 0;
452 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
454 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
457 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
458 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
460 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
461 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
463 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
465 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
467 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
502 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0);
503 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0);
505 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1);
506 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1);
527 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
529 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
605 md->md_v7.bt_solo = 0;
608 if (md->md_v7.rfe_type > 0)
613 md->md_v7.ant.diversity = 0;
628 md->md.bt_solo = 0;
631 if (md->md.rfe_type > 0)
636 md->md.ant.diversity = 0;
688 } while (0)
691 case 0xffff:
692 val = 0;
701 arg.ctrl_all_time != 0xffff);
704 case 0xffff:
705 val = 0;
713 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
799 .bbmcu_nr = 0,
800 .needed_fw_elms = 0,
806 .rsvd_ple_ofst = 0x2f800,
811 .rf_base_addr = {0xe000, 0xf000},
812 .thermal_th = {0x32, 0x35},
830 .support_link_num = 0,
831 .support_chanctx_num = 0,
861 .phycap_addr = 0x580,
863 .para_ver = 0,
864 .wlcx_desired = 0x05050000,
865 .btcx_desired = 0x5,
866 .scbd = 0x1,
867 .mailbox = 0x1,
882 .low_power_hci_modes = 0,