Lines Matching +full:0 +full:x000001ff
32 #define CHIP_PCIEIC 0x1900 /* PCIe Interrupt Cause */
33 #define CHIP_PCIEIM 0x1910 /* PCIe Interrupt Mask */
34 #define CHIP_PCIIC 0x1d58 /* PCI Interrupt Cause */
35 #define CHIP_PCIIM 0x1d5c /* PCI Interrupt Mask */
36 #define CHIP_MIC 0x1d60 /* Main Interrupt Cause */
37 #define CHIP_MIM 0x1d64 /* Main Interrupt Mask */
38 #define CHIP_SOC_MIC 0x20 /* SoC Main Interrupt Cause */
39 #define CHIP_SOC_MIM 0x24 /* SoC Main Interrupt Mask */
40 #define IC_ERR_IRQ (1 << 0) /* shift by (2 * port #) */
42 #define IC_HC0 0x000001ff /* bits 0-8 = HC0 */
45 #define IC_ERR_HC0 0x00000055 /* HC0 ERR_IRQ */
46 #define IC_DONE_HC0 0x000000aa /* HC0 DONE_IRQ */
58 #define IC_MAIN_RSVD (0xfe000000) /* bits 31-25 */
59 #define IC_MAIN_RSVD_5 (0xfff10000) /* bits 31-19 */
60 #define IC_MAIN_RSVD_SOC (0xfffffec0) /* bits 31-9, 7-6 */
62 #define CHIP_SOC_LED 0x2C /* SoC LED Configuration */
65 #define CHIP_SOC_HC0_MASK(num) (0xff >> ((4 - (num)) * 2))
68 #define CHIP_ICC 0x18008
70 #define CHIP_ICT 0x180cc
71 #define CHIP_ITT 0x180d0
72 #define CHIP_TRAN_COAL_CAUSE_LO 0x18088
73 #define CHIP_TRAN_COAL_CAUSE_HI 0x1808c
76 #define HC_SIZE 0x10000
77 #define HC_OFFSET 0x20000
80 #define HC_CFG 0x0 /* Configuration */
81 #define HC_CFG_TIMEOUT_MASK (0xff << 0)
87 #define HC_RQOP 0x4 /* Request Queue Out-Pointer */
88 #define HC_RQIP 0x8 /* Response Queue In-Pointer */
89 #define HC_ICT 0xc /* Interrupt Coalescing Threshold */
90 #define HC_ICT_SAICOALT_MASK 0x000000ff
91 #define HC_ITT 0x10 /* Interrupt Time Threshold */
92 #define HC_ITT_SAITMTH_MASK 0x00ffffff
93 #define HC_IC 0x14 /* Interrupt Cause */
99 #define PORT_SIZE 0x2000
100 #define PORT_OFFSET 0x2000
103 #define EDMA_CFG 0x0 /* Configuration */
104 #define EDMA_CFG_RESERVED (0x1f << 0) /* Queue len ? */
120 #define EDMA_T 0x4 /* Timer */
121 #define EDMA_IEC 0x8 /* Interrupt Error Cause */
122 #define EDMA_IEM 0xc /* Interrupt Error Mask */
130 #define EDMA_IE_LINKXERR_SATACRC (1 << 0) /* SATA CRC error */
145 #define EDMA_IE_TRANSIENT (EDMA_IE_LINKCTLRXERR(0x0b) | \
146 EDMA_IE_LINKCTLTXERR(0x1f))
148 #define EDMA_REQQBAH 0x10 /* Request Queue Base Address High */
149 #define EDMA_REQQIP 0x14 /* Request Queue In-Pointer */
150 #define EDMA_REQQOP 0x18 /* Request Queue Out-Pointer */
152 #define EDMA_REQQP_ERQQP_MASK 0x000003e0
153 #define EDMA_REQQP_ERQQBAP_MASK 0x00000c00
154 #define EDMA_REQQP_ERQQBA_MASK 0xfffff000
155 #define EDMA_RESQBAH 0x1c /* Response Queue Base Address High */
156 #define EDMA_RESQIP 0x20 /* Response Queue In-Pointer */
157 #define EDMA_RESQOP 0x24 /* Response Queue Out-Pointer */
159 #define EDMA_RESQP_ERPQP_MASK 0x000000f8
160 #define EDMA_RESQP_ERPQBAP_MASK 0x00000300
161 #define EDMA_RESQP_ERPQBA_MASK 0xfffffc00
162 #define EDMA_CMD 0x28 /* Command */
163 #define EDMA_CMD_EENEDMA (1 << 0) /* Enable EDMA */
167 #define EDMA_TC 0x2c /* Test Control */
168 #define EDMA_S 0x30 /* Status */
169 #define EDMA_S_EDEVQUETAG(s) ((s) & 0x0000001f)
170 #define EDMA_S_EDEVDIR_WRITE (0 << 5)
174 #define EDMA_S_ESTATE(s) (((s) & 0x0000ff00) >> 8)
175 #define EDMA_S_EIOID(s) (((s) & 0x003f0000) >> 16)
176 #define EDMA_IORT 0x34 /* IORdy Timeout */
177 #define EDMA_CDT 0x40 /* Command Delay Threshold */
178 #define EDMA_HC 0x60 /* Halt Condition */
179 #define EDMA_UNKN_RESD 0x6C /* Unknown register */
180 #define EDMA_CQDCQOS(x) (0x90 + ((x) << 2)
184 #define ATA_DATA 0x100 /* (RW) data */
185 #define ATA_FEATURE 0x104 /* (W) feature */
186 #define ATA_F_DMA 0x01 /* enable DMA */
187 #define ATA_F_OVL 0x02 /* enable overlap */
188 #define ATA_ERROR 0x104 /* (R) error */
189 #define ATA_E_ILI 0x01 /* illegal length */
190 #define ATA_E_NM 0x02 /* no media */
191 #define ATA_E_ABORT 0x04 /* command aborted */
192 #define ATA_E_MCR 0x08 /* media change request */
193 #define ATA_E_IDNF 0x10 /* ID not found */
194 #define ATA_E_MC 0x20 /* media changed */
195 #define ATA_E_UNC 0x40 /* uncorrectable data */
196 #define ATA_E_ICRC 0x80 /* UDMA crc error */
197 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
198 #define ATA_COUNT 0x108 /* (W) sector count */
199 #define ATA_IREASON 0x108 /* (R) interrupt reason */
200 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
201 #define ATA_I_IN 0x02 /* read (1) | write (0) */
202 #define ATA_I_RELEASE 0x04 /* released bus (1) */
203 #define ATA_I_TAGMASK 0xf8 /* tag mask */
204 #define ATA_SECTOR 0x10c /* (RW) sector # */
205 #define ATA_CYL_LSB 0x110 /* (RW) cylinder# LSB */
206 #define ATA_CYL_MSB 0x114 /* (RW) cylinder# MSB */
207 #define ATA_DRIVE 0x118 /* (W) Sector/Drive/Head */
208 #define ATA_D_LBA 0x40 /* use LBA addressing */
209 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
210 #define ATA_COMMAND 0x11c /* (W) command */
211 #define ATA_STATUS 0x11c /* (R) status */
212 #define ATA_S_ERROR 0x01 /* error */
213 #define ATA_S_INDEX 0x02 /* index */
214 #define ATA_S_CORR 0x04 /* data corrected */
215 #define ATA_S_DRQ 0x08 /* data request */
216 #define ATA_S_DSC 0x10 /* drive seek completed */
217 #define ATA_S_SERVICE 0x10 /* drive needs service */
218 #define ATA_S_DWF 0x20 /* drive write fault */
219 #define ATA_S_DMA 0x20 /* DMA ready */
220 #define ATA_S_READY 0x40 /* drive ready */
221 #define ATA_S_BUSY 0x80 /* busy */
222 #define ATA_CONTROL 0x120 /* (W) control */
223 #define ATA_A_IDS 0x02 /* disable interrupts */
224 #define ATA_A_RESET 0x04 /* RESET controller */
225 #define ATA_A_4BIT 0x08 /* 4 head bits */
226 #define ATA_A_HOB 0x80 /* High Order Byte enable */
227 #define ATA_ALTSTAT 0x120 /* (R) alternate status */
233 #define ATAPI_P_ABORT 0
236 #define DMA_C 0x224 /* Basic DMA Command */
237 #define DMA_C_START (1 << 0)
242 #define DMA_C_DRBC(n) (((n) & 0xffff) << 16)
243 #define DMA_S 0x228 /* Basic DMA Status */
244 #define DMA_S_ACT (1 << 0) /* Active */
248 #define DMA_DTLBA 0x22c /* Descriptor Table Low Base Address */
249 #define DMA_DTLBA_MASK 0xfffffff0
250 #define DMA_DTHBA 0x230 /* Descriptor Table High Base Address */
251 #define DMA_DRLA 0x234 /* Data Region Low Address */
252 #define DMA_DRHA 0x238 /* Data Region High Address */
255 #define SATA_SS 0x300 /* SStatus */
256 #define SATA_SS_DET_MASK 0x0000000f
257 #define SATA_SS_DET_NO_DEVICE 0x00000000
258 #define SATA_SS_DET_DEV_PRESENT 0x00000001
259 #define SATA_SS_DET_PHY_ONLINE 0x00000003
260 #define SATA_SS_DET_PHY_OFFLINE 0x00000004
262 #define SATA_SS_SPD_MASK 0x000000f0
263 #define SATA_SS_SPD_NO_SPEED 0x00000000
264 #define SATA_SS_SPD_GEN1 0x00000010
265 #define SATA_SS_SPD_GEN2 0x00000020
266 #define SATA_SS_SPD_GEN3 0x00000030
268 #define SATA_SS_IPM_MASK 0x00000f00
269 #define SATA_SS_IPM_NO_DEVICE 0x00000000
270 #define SATA_SS_IPM_ACTIVE 0x00000100
271 #define SATA_SS_IPM_PARTIAL 0x00000200
272 #define SATA_SS_IPM_SLUMBER 0x00000600
273 #define SATA_SE 0x304 /* SError */
274 #define SATA_SEIM 0x340 /* SError Interrupt Mask */
275 #define SATA_SE_DATA_CORRECTED 0x00000001
276 #define SATA_SE_COMM_CORRECTED 0x00000002
277 #define SATA_SE_DATA_ERR 0x00000100
278 #define SATA_SE_COMM_ERR 0x00000200
279 #define SATA_SE_PROT_ERR 0x00000400
280 #define SATA_SE_HOST_ERR 0x00000800
281 #define SATA_SE_PHY_CHANGED 0x00010000
282 #define SATA_SE_PHY_IERROR 0x00020000
283 #define SATA_SE_COMM_WAKE 0x00040000
284 #define SATA_SE_DECODE_ERR 0x00080000
285 #define SATA_SE_PARITY_ERR 0x00100000
286 #define SATA_SE_CRC_ERR 0x00200000
287 #define SATA_SE_HANDSHAKE_ERR 0x00400000
288 #define SATA_SE_LINKSEQ_ERR 0x00800000
289 #define SATA_SE_TRANSPORT_ERR 0x01000000
290 #define SATA_SE_UNKNOWN_FIS 0x02000000
291 #define SATA_SC 0x308 /* SControl */
292 #define SATA_SC_DET_MASK 0x0000000f
293 #define SATA_SC_DET_IDLE 0x00000000
294 #define SATA_SC_DET_RESET 0x00000001
295 #define SATA_SC_DET_DISABLE 0x00000004
297 #define SATA_SC_SPD_MASK 0x000000f0
298 #define SATA_SC_SPD_NO_SPEED 0x00000000
299 #define SATA_SC_SPD_SPEED_GEN1 0x00000010
300 #define SATA_SC_SPD_SPEED_GEN2 0x00000020
301 #define SATA_SC_SPD_SPEED_GEN3 0x00000030
303 #define SATA_SC_IPM_MASK 0x00000f00
304 #define SATA_SC_IPM_NONE 0x00000000
305 #define SATA_SC_IPM_DIS_PARTIAL 0x00000100
306 #define SATA_SC_IPM_DIS_SLUMBER 0x00000200
308 #define SATA_SC_SPM_MASK 0x0000f000
309 #define SATA_SC_SPM_NONE 0x00000000
310 #define SATA_SC_SPM_PARTIAL 0x00001000
311 #define SATA_SC_SPM_SLUMBER 0x00002000
312 #define SATA_SC_SPM_ACTIVE 0x00004000
313 #define SATA_LTM 0x30c /* LTMode */
314 #define SATA_PHYM3 0x310 /* PHY Mode 3 */
315 #define SATA_PHYM4 0x314 /* PHY Mode 4 */
316 #define SATA_PHYM1 0x32c /* PHY Mode 1 */
317 #define SATA_PHYM2 0x330 /* PHY Mode 2 */
318 #define SATA_BISTC 0x334 /* BIST Control */
319 #define SATA_BISTDW1 0x338 /* BIST DW1 */
320 #define SATA_BISTDW2 0x33c /* BIST DW2 */
321 #define SATA_SATAICFG 0x050 /* Serial-ATA Interface Configuration */
322 #define SATA_SATAICFG_REFCLKCNF_20MHZ (0 << 0)
323 #define SATA_SATAICFG_REFCLKCNF_25MHZ (1 << 0)
324 #define SATA_SATAICFG_REFCLKCNF_30MHZ (2 << 0)
325 #define SATA_SATAICFG_REFCLKCNF_40MHZ (3 << 0)
326 #define SATA_SATAICFG_REFCLKCNF_MASK (3 << 0)
327 #define SATA_SATAICFG_REFCLKDIV_1 (0 << 2)
332 #define SATA_SATAICFG_REFCLKFEEDDIV_50 (0 << 4) /* or 100, when Gen2En is 1 */
346 #define SATA_SATAICTL 0x344 /* Serial-ATA Interface Control */
347 #define SATA_SATAICTL_PMPTX_MASK 0x0000000f
348 #define SATA_SATAICTL_PMPTX_SHIFT 0
354 #define SATA_SATAITC 0x348 /* Serial-ATA Interface Test Control */
355 #define SATA_SATAIS 0x34c /* Serial-ATA Interface Status */
356 #define SATA_VU 0x35c /* Vendor Unique */
357 #define SATA_FISC 0x360 /* FIS Configuration */
358 #define SATA_FISC_FISWAIT4RDYEN_B0 (1 << 0) /* Device to Host FIS */
359 #define SATA_FISC_FISWAIT4RDYEN_B1 (1 << 1) /* SDB FIS rcv with <N>bit 0 */
375 #define SATA_FISIC 0x364 /* FIS Interrupt Cause */
376 #define SATA_FISIM 0x368 /* FIS Interrupt Mask */
377 #define SATA_FISDW0 0x370 /* FIS DW0 */
378 #define SATA_FISDW1 0x374 /* FIS DW1 */
379 #define SATA_FISDW2 0x378 /* FIS DW2 */
380 #define SATA_FISDW3 0x37c /* FIS DW3 */
381 #define SATA_FISDW4 0x380 /* FIS DW4 */
382 #define SATA_FISDW5 0x384 /* FIS DW5 */
383 #define SATA_FISDW6 0x388 /* FIS DW6 */
385 #define SATA_PHYM9_GEN2 0x398
386 #define SATA_PHYM9_GEN1 0x39c
387 #define SATA_PHYCFG_OFS 0x3a0 /* 65nm SoCs only */
400 #define MVS_CRQB_READ 0x0001
401 #define MVS_CRQB_TAG_MASK 0x003e
403 #define MVS_CRQB_PMP_MASK 0xf000
412 #define MVS_CRQB2E_READ 0x00000001
413 #define MVS_CRQB2E_DTAG_MASK 0x0000003e
415 #define MVS_CRQB2E_PMP_MASK 0x0000f000
417 #define MVS_CRQB2E_CPRD 0x00010000
418 #define MVS_CRQB2E_HTAG_MASK 0x003e0000
428 #define MVS_EPRD_MASK 0x0000ffff /* max 64KB */
430 #define MVS_EPRD_EOF 0x80000000
436 #define MVS_CRQB_OFFSET 0
438 #define MVS_CRQB_MASK 0x000003e0
451 #define MVS_CRPB_TAG_MASK 0x001F
452 #define MVS_CRPB_TAG_SHIFT 0
454 #define MVS_CRPB_EDMASTS_MASK 0x007F
455 #define MVS_CRPB_EDMASTS_SHIFT 0
456 #define MVS_CRPB_ATASTS_MASK 0xFF00
462 #define MVS_CRPB_OFFSET 0
464 #define MVS_CRPB_MASK 0x000000f8
472 #define ATA_IRQ_RID 0