Lines Matching +full:0 +full:x000001ff
41 #define TGEC_TX_IPG_LENGTH_MASK 0x000003ff
73 #define CMD_CFG_EN_TIMESTAMP 0x00100000
74 #define CMD_CFG_TX_ADDR_INS_SEL 0x00080000
75 #define CMD_CFG_NO_LEN_CHK 0x00020000
76 #define CMD_CFG_SEND_IDLE 0x00010000
77 #define CMD_CFG_RX_ER_DISC 0x00004000
78 #define CMD_CFG_CMD_FRM_EN 0x00002000
79 #define CMD_CFG_STAT_CLR 0x00001000
80 #define CMD_CFG_LOOPBACK_EN 0x00000400
81 #define CMD_CFG_TX_ADDR_INS 0x00000200
82 #define CMD_CFG_PAUSE_IGNORE 0x00000100
83 #define CMD_CFG_PAUSE_FWD 0x00000080
84 #define CMD_CFG_PROMIS_EN 0x00000010
85 #define CMD_CFG_WAN_MODE 0x00000008
86 #define CMD_CFG_RX_EN 0x00000002
87 #define CMD_CFG_TX_EN 0x00000001
90 #define TGEC_IMASK_MDIO_SCAN_EVENT 0x00010000
91 #define TGEC_IMASK_MDIO_CMD_CMPL 0x00008000
92 #define TGEC_IMASK_REM_FAULT 0x00004000
93 #define TGEC_IMASK_LOC_FAULT 0x00002000
94 #define TGEC_IMASK_TX_ECC_ER 0x00001000
95 #define TGEC_IMASK_TX_FIFO_UNFL 0x00000800
96 #define TGEC_IMASK_TX_FIFO_OVFL 0x00000400
97 #define TGEC_IMASK_TX_ER 0x00000200
98 #define TGEC_IMASK_RX_FIFO_OVFL 0x00000100
99 #define TGEC_IMASK_RX_ECC_ER 0x00000080
100 #define TGEC_IMASK_RX_JAB_FRM 0x00000040
101 #define TGEC_IMASK_RX_OVRSZ_FRM 0x00000020
102 #define TGEC_IMASK_RX_RUNT_FRM 0x00000010
103 #define TGEC_IMASK_RX_FRAG_FRM 0x00000008
104 #define TGEC_IMASK_RX_LEN_ER 0x00000004
105 #define TGEC_IMASK_RX_CRC_ER 0x00000002
106 #define TGEC_IMASK_RX_ALIGN_ER 0x00000001
129 #define TGEC_HASH_MCAST_EN 0x00000200
130 #define TGEC_HASH_ADR_MSK 0x000001ff
145 #define DEFAULT_MAX_FRAME_LENGTH 0x600
146 #define DEFAULT_PAUSE_QUANT 0xf000
152 uint32_t tgec_id; /* 0x000 Controller ID */
153 uint32_t reserved001[1]; /* 0x004 */
154 uint32_t command_config; /* 0x008 Control and configuration */
155 uint32_t mac_addr_0; /* 0x00c Lower 32 bits of the MAC adr */
156 uint32_t mac_addr_1; /* 0x010 Upper 16 bits of the MAC adr */
157 uint32_t maxfrm; /* 0x014 Maximum frame length */
158 uint32_t pause_quant; /* 0x018 Pause quanta */
159 uint32_t rx_fifo_sections; /* 0x01c */
160 uint32_t tx_fifo_sections; /* 0x020 */
161 uint32_t rx_fifo_almost_f_e; /* 0x024 */
162 uint32_t tx_fifo_almost_f_e; /* 0x028 */
163 uint32_t hashtable_ctrl; /* 0x02c Hash table control*/
164 uint32_t mdio_cfg_status; /* 0x030 */
165 uint32_t mdio_command; /* 0x034 */
166 uint32_t mdio_data; /* 0x038 */
167 uint32_t mdio_regaddr; /* 0x03c */
168 uint32_t status; /* 0x040 */
169 uint32_t tx_ipg_len; /* 0x044 Transmitter inter-packet-gap */
170 uint32_t mac_addr_2; /* 0x048 Lower 32 bits of 2nd MAC adr */
171 uint32_t mac_addr_3; /* 0x04c Upper 16 bits of 2nd MAC adr */
172 uint32_t rx_fifo_ptr_rd; /* 0x050 */
173 uint32_t rx_fifo_ptr_wr; /* 0x054 */
174 uint32_t tx_fifo_ptr_rd; /* 0x058 */
175 uint32_t tx_fifo_ptr_wr; /* 0x05c */
176 uint32_t imask; /* 0x060 Interrupt mask */
177 uint32_t ievent; /* 0x064 Interrupt event */
178 uint32_t udp_port; /* 0x068 Defines a UDP Port number */
179 uint32_t type_1588v2; /* 0x06c Type field for 1588v2 */
180 uint32_t reserved070[4]; /* 0x070 */
259 * When set to 0 (Reset value), erroneous Frames are
263 * frames are ignored by the MAC. When set to 0
270 * to 0 (Reset value) pause frames are terminated and
273 * Payload Length Check Disable. When set to 0
278 * all Command Frames are accepted, when set to 0
285 * (0, default) of operation.
289 * when set to 0 (Reset value) Unicast Frames with a
297 * to 0 (Reset value), the source MAC address from the
300 * loop_ena is set to '1', when set to 0 (Reset value)
301 * the signal loop_ena is set to 0.
306 * 0: IEEE 1588 is disabled
309 * to 16,352 bytes (0x3FE0). Typical settings are
310 * 0x05EE (1,518 bytes) for standard frames.
311 * Default setting is 0x0600 (1,536 bytes).
365 * Returns: 0 if successful, an error code otherwise.
418 * 0 - MAC stops transmit process for the duration specified
431 * 0 disabled, 1 enabled