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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dmba8xx.dtsi15 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
26 pinctrl-0 = <&pinctrl_bl_lvds>;
27 pwms = <&adma_pwm 0 5000000 0>;
28 brightness-levels = <0 4 8 16 32 64 128 255>;
42 pinctrl-0 = <&pinctrl_gpiobuttons>;
91 pinctrl-0 = <&pinctrl_reg_pcie_1v5>;
103 pinctrl-0 = <&pinctrl_reg_pcie_3v3>;
129 pinctrl-0 = <&pinctrl_adc0>;
137 pinctrl-0 = <&pinctrl_admapwm>;
142 pinctrl-0 = <&pinctrl_fec1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf700t.dts92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "
[all...]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/freebsd/sys/dev/ale/
H A Dif_alereg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR81XX 0x1026
43 #define ALE_SPI_CTRL 0x200
44 #define SPI_VPD_ENB 0x00002000
46 #define ALE_SPI_ADDR 0x204 /* 16bits */
48 #define ALE_SPI_DATA 0x208
50 #define ALE_SPI_CONFIG 0x20C
52 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */
54 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */
56 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */
[all …]
/freebsd/sys/dev/nge/
H A Dif_ngereg.h36 #define NGE_CSR 0x00
37 #define NGE_CFG 0x04
38 #define NGE_MEAR 0x08
39 #define NGE_PCITST 0x0C
40 #define NGE_ISR 0x10
41 #define NGE_IMR 0x14
42 #define NGE_IER 0x18
43 #define NGE_IHR 0x1C
44 #define NGE_TX_LISTPTR_LO 0x20
45 #define NGE_TX_LISTPTR_HI 0x24
[all …]
/freebsd/sys/dev/jme/
H A Dif_jmereg.h36 #define VENDORID_JMICRON 0x197B
41 #define DEVICEID_JMC250 0x0250
42 #define DEVICEREVID_JMC250_A0 0x00
43 #define DEVICEREVID_JMC250_A2 0x11
48 #define DEVICEID_JMC260 0x0260
49 #define DEVICEREVID_JMC260_A0 0x00
51 #define DEVICEID_JMC2XX_MASK 0x0FF0
54 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */
56 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */
58 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */
[all …]
/freebsd/sys/contrib/device-tree/src/nios2/
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/
H A Dr92c_tx_desc.h28 #define R92C_FLAGS0_BMCAST 0x01
29 #define R92C_FLAGS0_LSG 0x04
30 #define R92C_FLAGS0_FSG 0x08
31 #define R92C_FLAGS0_OWN 0x80
34 #define R92C_TXDW1_MACID_M 0x0000001f
35 #define R92C_TXDW1_MACID_S 0
36 #define R92C_TXDW1_AGGEN 0x00000020
37 #define R92C_TXDW1_AGGBK 0x00000040
39 #define R92C_TXDW1_QSEL_M 0x00001f00
42 #define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 */
[all …]
/freebsd/sys/dev/sound/pci/
H A Dcs4281.h32 #define CS4281_PCI_ID 0x60051013
39 #define CS4281PCI_HISR 0x000
40 # define CS4281PCI_HISR_DMAI 0x00040000
41 # define CS4281PCI_HISR_DMA(x) (0x0100 << (x))
43 #define CS4281PCI_HICR 0x008
44 # define CS4281PCI_HICR_EOI 0x00000003
46 #define CS4281PCI_HIMR 0x00c
47 # define CS4281PCI_HIMR_DMAI 0x00040000
48 # define CS4281PCI_HIMR_DMA(x) (0x0100 << (x))
50 #define CS4281PCI_IIER 0x010
[all …]
/freebsd/sys/dev/sis/
H A Dif_sisreg.h45 #define SIS_CSR 0x00
46 #define SIS_CFG 0x04
47 #define SIS_EECTL 0x08
48 #define SIS_PCICTL 0x0C
49 #define SIS_ISR 0x10
50 #define SIS_IMR 0x14
51 #define SIS_IER 0x18
52 #define SIS_PHYCTL 0x1C
53 #define SIS_TX_LISTPTR 0x20
54 #define SIS_TX_CFG 0x24
[all …]
/freebsd/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmureg.h29 (((_value) & _flag) != 0)
43 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
55 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
56 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
57 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
58 #define BHND_CCS_FORCE_MASK 0x0000000F
60 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
61 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
62 #define BHND_CCS_AREQ_MASK 0x00000018
64 #define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_dcb_82598.h41 #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin,
43 #define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */
44 #define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */
45 #define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
47 #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
50 #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
52 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet
54 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores
59 #define IXGBE_TDTQ2TCCR_GSP 0x40000000
60 #define IXGBE_TDTQ2TCCR_LSP 0x80000000
[all …]
H A Dixgbe_dcb_82599.h39 #define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin,
42 #define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin,
45 #define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */
46 #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */
47 #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must
50 #define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */
60 #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */
61 #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */
63 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet
66 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores
[all …]
/freebsd/sys/dev/age/
H A Dif_agereg.h36 #define VENDORID_ATTANSIC 0x1969
41 #define DEVICEID_ATTANSIC_L1 0x1048
43 #define AGE_VPD_REG_CONF_START 0x0100
44 #define AGE_VPD_REG_CONF_END 0x01FF
45 #define AGE_VPD_REG_CONF_SIG 0x5A
47 #define AGE_SPI_CTRL 0x200
48 #define SPI_STAT_NOT_READY 0x00000001
49 #define SPI_STAT_WR_ENB 0x00000002
50 #define SPI_STAT_WRP_ENB 0x00000080
51 #define SPI_INST_MASK 0x000000FF
[all …]
/freebsd/sys/powerpc/include/
H A Dtlb.h36 #define MAS0_TLBSEL(x) ((x << 28) & 0x10000000)
37 #define MAS0_ESEL(x) ((x << 16) & 0x003F0000)
39 #define MAS0_TLBSEL1 0x10000000
40 #define MAS0_TLBSEL0 0x00000000
41 #define MAS0_ESEL_TLB1MASK 0x000F0000
42 #define MAS0_ESEL_TLB0MASK 0x00030000
44 #define MAS0_NV_MASK 0x00000003
45 #define MAS0_NV_SHIFT 0
47 #define MAS1_VALID 0x80000000
48 #define MAS1_IPROT 0x40000000
[all …]
/freebsd/sys/dev/gem/
H A Dif_gemreg.h37 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
38 #define GEM_CONFIG 0x0004 /* config reg */
39 #define GEM_STATUS 0x000c /* status reg */
40 /* Note: Reading the status reg clears bits 0-6. */
41 #define GEM_INTMASK 0x0010
42 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
43 #define GEM_STATUS_ALIAS 0x001c
46 #define GEM_SEB_ARB 0x00000002 /* Arbitration status */
47 #define GEM_SEB_RXWON 0x00000004
50 #define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */
[all …]
/freebsd/sys/dev/lge/
H A Dif_lgereg.h37 #define LGE_MODE1 0x00 /* CSR00 */
38 #define LGE_MODE2 0x04 /* CSR01 */
39 #define LGE_PPTXBUF_IDX 0x08 /* CSR02 */
40 #define LGE_PRODID 0x0C /* CSR03 */
41 #define LGE_PPTXBUF_ADDR_LO 0x10 /* CSR04 */
42 #define LGE_PPTXBUF_ADDR_HI 0x14 /* CSR05 */
43 #define LGE_RSVD0 0x18 /* CSR06 */
44 #define LGE_PPRXBUF_IDX 0x1C /* CSR07 */
45 #define LGE_PPRXBUF_ADDR_LO 0x20 /* CSR08 */
46 #define LGE_PPRXBUF_ADDR_HI 0x24 /* CSR09 */
[all …]
/freebsd/sys/dev/alc/
H A Dif_alcreg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
[all …]
/freebsd/sys/dev/et/
H A Dif_etreg.h57 #define ET_PCIR_DEVICE_CAPS 0x4C
58 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */
59 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0
60 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1
62 #define ET_PCIR_DEVICE_CTRL 0x50
63 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */
64 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000
66 #define ET_PCIR_MAC_ADDR0 0xA4
67 #define ET_PCIR_MAC_ADDR1 0xA8
69 #define ET_PCIR_EEPROM_STATUS 0xB2 /* XXX undocumented */
[all …]
/freebsd/sys/x86/include/
H A Dspecialreg.h38 #define CR0_PE 0x00000001 /* Protected mode Enable */
39 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
40 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
41 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
42 #define CR0_PG 0x80000000 /* PaGing enable */
47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
48 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
50 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
51 #define CR0_NW 0x20000000 /* Not Write-through */
52 #define CR0_CD 0x40000000 /* Cache Disable */
[all …]
/freebsd/sys/dev/dc/
H A Dif_dcreg.h39 #define DC_BUSCTL 0x00 /* bus control */
40 #define DC_TXSTART 0x08 /* tx start demand */
41 #define DC_RXSTART 0x10 /* rx start demand */
42 #define DC_RXADDR 0x18 /* rx descriptor list start addr */
43 #define DC_TXADDR 0x20 /* tx descriptor list start addr */
44 #define DC_ISR 0x28 /* interrupt status register */
45 #define DC_NETCFG 0x30 /* network config register */
46 #define DC_IMR 0x38 /* interrupt mask */
47 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
48 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */
[all …]

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