| /linux/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/ |
| H A D | uncore-cpa.json | 3 "ConfigCode": "0x00",
6 "Compat": "0x00000030",
10 "ConfigCode": "0x61",
13 "Compat": "0x00000030",
17 "ConfigCode": "0x62",
20 "Compat": "0x00000030",
24 "ConfigCode": "0x3",
27 "Compat": "0x00000030",
31 "ConfigCode": "0x4",
34 "Compat": "0x00000030",
[all …]
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| /linux/drivers/net/wireless/realtek/rtw88/ |
| H A D | rtw8822c_table.c | 16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]
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| /linux/drivers/bcma/ |
| H A D | scan.h | 5 #define BCMA_ADDR_BASE 0x18000000
6 #define BCMA_WRAP_BASE 0x18100000
8 #define SCAN_ER_VALID 0x00000001
9 #define SCAN_ER_TAGX 0x00000006 /* we have to ignore 0x8 bit when checking tag for SCAN_ER_TAG_ADD…
10 #define SCAN_ER_TAG 0x0000000E
11 #define SCAN_ER_TAG_CI 0x00000000
12 #define SCAN_ER_TAG_MP 0x00000002
13 #define SCAN_ER_TAG_ADDR 0x00000004
14 #define SCAN_ER_TAG_END 0x0000000E
15 #define SCAN_ER_BAD 0xFFFFFFFF
[all …]
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| /linux/arch/parisc/include/uapi/asm/ |
| H A D | termbits.h | 42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x4000
65 #define IUTF8 0x8000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
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| /linux/include/uapi/asm-generic/ |
| H A D | termbits.h | 42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x2000
65 #define IUTF8 0x4000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
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| /linux/drivers/video/fbdev/mb862xx/ |
| H A D | mb862xx_reg.h | 9 #define MB862XX_MMIO_BASE 0x01fc0000
10 #define MB862XX_MMIO_HIGH_BASE 0x03fc0000
11 #define MB862XX_I2C_BASE 0x0000c000
12 #define MB862XX_DISP_BASE 0x00010000
13 #define MB862XX_CAP_BASE 0x00018000
14 #define MB862XX_DRAW_BASE 0x00030000
15 #define MB862XX_GEO_BASE 0x00038000
16 #define MB862XX_PIO_BASE 0x00038000
17 #define MB862XX_MMIO_SIZE 0x40000
20 #define GC_IST 0x00000020
[all …]
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| /linux/arch/sparc/include/uapi/asm/ |
| H A D | perfctr.h | 58 #define PRIV 0x00000001
59 #define SYS 0x00000002
60 #define USR 0x00000004
63 #define CYCLE_CNT 0x00000000
64 #define INSTR_CNT 0x00000010
65 #define DISPATCH0_IC_MISS 0x00000020
66 #define DISPATCH0_STOREBUF 0x00000030
67 #define IC_REF 0x00000080
68 #define DC_RD 0x00000090
69 #define DC_WR 0x000000A0
[all …]
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| /linux/arch/m68k/include/asm/ |
| H A D | m54xxgpt.h | 20 #define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
21 #define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
22 #define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
23 #define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
24 #define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
25 #define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
26 #define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
27 #define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
28 #define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
29 #define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)
[all …]
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| /linux/arch/powerpc/include/asm/nohash/32/ |
| H A D | mmu-44x.h | 10 #define PPC44x_MMUCR_TID 0x000000ff
11 #define PPC44x_MMUCR_STS 0x00010000
13 #define PPC44x_TLB_PAGEID 0
18 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
19 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
20 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */
21 #define PPC44x_TLB_1K 0x00000000 /* Page sizes */
22 #define PPC44x_TLB_4K 0x00000010
23 #define PPC44x_TLB_16K 0x00000020
24 #define PPC44x_TLB_64K 0x00000030
[all …]
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| /linux/drivers/media/pci/ddbridge/ |
| H A D | ddbridge-mci.h | 15 #define DEMOD_UNUSED (0xFF)
17 #define MCI_CONTROL (0x500)
18 #define MCI_COMMAND (0x600)
19 #define MCI_RESULT (0x680)
21 #define MCI_COMMAND_SIZE (0x80)
22 #define MCI_RESULT_SIZE (0x80)
24 #define MCI_CONTROL_START_COMMAND (0x00000001)
25 #define MCI_CONTROL_ENABLE_DONE_INTERRUPT (0x00000002)
26 #define MCI_CONTROL_RESET (0x00008000)
27 #define MCI_CONTROL_READY (0x00010000)
[all …]
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | vic.h | 11 #define VIC_SET_FCE_UCODE_SIZE 0x0000071C
12 #define VIC_SET_FCE_UCODE_OFFSET 0x0000072C
16 #define VIC_THI_STREAMID0 0x00000030
17 #define VIC_THI_STREAMID1 0x00000034
19 #define NV_PVIC_MISC_PRI_VIC_CG 0x000016d0
20 #define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0)
22 #define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16)
24 #define VIC_TFBIF_TRANSCFG 0x00002044
25 #define TRANSCFG_ATT(i, v) (((v) & 0x3) << (i * 4))
26 #define TRANSCFG_SID_HW 0
|
| /linux/arch/mips/include/uapi/asm/ |
| H A D | termbits.h | 55 #define VINTR 0 /* Interrupt character [ISIG] */
67 #if 0
81 #define IUCLC 0x0200 /* Map upper case to lower case on input */
82 #define IXON 0x0400 /* Enable start/stop output control */
83 #define IXOFF 0x1000 /* Enable start/stop input control */
84 #define IMAXBEL 0x2000 /* Ring bell when input queue is full */
85 #define IUTF8 0x4000 /* Input is UTF-8 */
88 #define OLCUC 0x00002 /* Map lower case to upper case on output */
89 #define ONLCR 0x00004 /* Map NL to CR-NL on output */
90 #define NLDLY 0x00100
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | mcp77.c | 45 return nvkm_rd32(device, 0x004600); in read_div()
52 u32 ctrl = nvkm_rd32(device, base + 0); in read_pll()
55 u32 post_div = 0; in read_pll()
56 u32 clock = 0; in read_pll()
60 case 0x4020: in read_pll()
61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll()
63 case 0x4028: in read_pll()
64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll()
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
71 M1 = (coef & 0x000000ff); in read_pll()
[all …]
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| /linux/arch/mips/ath25/ |
| H A D | ar5312_regs.h | 17 #define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
18 #define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
19 #define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
20 #define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
21 #define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
26 #define AR5312_MISC_IRQ_TIMER 0
41 * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
44 #define AR5312_WLAN0_BASE 0x18000000
45 #define AR5312_ENET0_BASE 0x18100000
46 #define AR5312_ENET1_BASE 0x18200000
[all …]
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| /linux/drivers/net/ethernet/ |
| H A D | jme.h | 19 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
20 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
38 if (0) \
40 } while (0)
46 #define PCI_DCSR_MRRS 0x59
47 #define PCI_DCSR_MRRS_MASK 0x70
50 MRRS_128B = 0x00,
51 MRRS_256B = 0x10,
52 MRRS_512B = 0x20,
53 MRRS_1024B = 0x30,
[all …]
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| /linux/arch/mips/include/asm/txx9/ |
| H A D | tx4927.h | 36 #define TX4927_REG_BASE 0xffffffffff1f0000UL
38 #define TX4927_REG_BASE 0xff1f0000UL
40 #define TX4927_REG_SIZE 0x00010000
42 #define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43 #define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44 #define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)
45 #define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
46 #define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
47 #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
49 #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/ |
| H A D | nv50.c | 59 if ((ctx->outp[0] & 0x0000000f) != ctx->desc.outp_type) in mxm_match_dcb()
66 if ((desc & 0x00000000000000f0) >= 0x20) { in mxm_match_dcb()
69 if ((ctx->outp[0] & 0x0f000000) != (link & 0x0f) << 24) in mxm_match_dcb()
73 link = (link & 0x30) >> 4; in mxm_match_dcb()
74 if ((link & ((ctx->outp[1] & 0x00000030) >> 4)) != link) in mxm_match_dcb()
83 data[0] &= ~0xf0; in mxm_match_dcb()
85 mxms_foreach(mxm, 0x01, mxm_match_tmds_partner, ctx)) { in mxm_match_dcb()
86 data[0] |= 0x20; /* modify descriptor to match TMDS now */ in mxm_match_dcb()
88 data[0] |= 0xf0; in mxm_match_dcb()
105 if (mxms_foreach(mxm, 0x01, mxm_match_dcb, &ctx)) { in mxm_dcb_sanitise_entry()
[all …]
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| /linux/drivers/net/ethernet/smsc/ |
| H A D | smsc911x.h | 12 #define LAN9115 0x01150000
13 #define LAN9116 0x01160000
14 #define LAN9117 0x01170000
15 #define LAN9118 0x01180000
16 #define LAN9215 0x115A0000
17 #define LAN9216 0x116A0000
18 #define LAN9217 0x117A0000
19 #define LAN9218 0x118A0000
20 #define LAN9210 0x92100000
21 #define LAN9211 0x92110000
[all …]
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| /linux/drivers/staging/rtl8723bs/hal/ |
| H A D | HalHWImg8723B_MAC.c | 16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
31 pDM_Odm->TypeGLNA << 0 | in CheckPositive()
40 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) in CheckPositive()
42 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) in CheckPositive()
48 cond1 &= 0x000F0FFF; in CheckPositive()
49 driver1 &= 0x000F0FFF; in CheckPositive()
52 u32 bitMask = 0; in CheckPositive()
53 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE */ in CheckPositive()
56 if ((cond1 & BIT0) != 0) /* GLNA */ in CheckPositive()
57 bitMask |= 0x000000FF; in CheckPositive()
[all …]
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| /linux/drivers/gpu/drm/mcde/ |
| H A D | mcde_dsi_regs.h | 5 #define DSI_MCTL_INTEGRATION_MODE 0x00000000
7 #define DSI_MCTL_MAIN_DATA_CTL 0x00000004
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
25 #define DSI_MCTL_MAIN_PHY_CTL 0x00000008
26 #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0)
33 #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0
36 #define DSI_MCTL_PLL_CTL 0x0000000C
37 #define DSI_MCTL_LANE_STS 0x00000010
39 #define DSI_MCTL_DPHY_TIMEOUT 0x00000014
40 #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0
[all …]
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| /linux/arch/powerpc/include/asm/ |
| H A D | fsl_lbc.h | 22 #define BR_BA 0xFFFF8000
24 #define BR_PS 0x00001800
26 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
27 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
28 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
29 #define BR_DECC 0x00000600
31 #define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
32 #define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
33 #define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
34 #define BR_WP 0x00000100
[all …]
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| /linux/drivers/of/unittest-data/ |
| H A D | overlay_common.dtsi | 19 reg = <0x00000100 0x100>;
50 reg = <0x00000100 0x100>;
60 reg = <0x00000030 0x10>;
64 reg = <0x00000040 0x10>;
72 reg = <0x00030000 0x1000>;
78 reg = <0x00040000 0x1000>;
84 reg = <0x00050000 0x1000>;
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| /linux/drivers/net/ethernet/samsung/sxgbe/ |
| H A D | sxgbe_mtl.h | 12 #define SXGBE_MTL_OPMODE_ESTMASK 0x3
13 #define SXGBE_MTL_OPMODE_RAAMASK 0x1
14 #define SXGBE_MTL_FCMASK 0x7
20 #define SXGBE_MTL_ENABLE_FC 0x80
22 #define ETS_WRR 0xFFFFFF9F
23 #define ETS_RST 0xFFFFFF9F
24 #define ETS_WFQ 0x00000020
25 #define ETS_DWRR 0x00000040
26 #define RAA_SP 0xFFFFFFFB
27 #define RAA_WSP 0x00000004
[all …]
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| /linux/drivers/gpu/drm/etnaviv/ |
| H A D | state.xml.h | 7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define VARYING_COMPONENT_USE_UNUSED 0x00000000
49 #define VARYING_COMPONENT_USE_USED 0x00000001
50 #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002
51 #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003
52 #define FE_DATA_TYPE_BYTE 0x00000000
53 #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001
54 #define FE_DATA_TYPE_SHORT 0x00000002
55 #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
[all …]
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| /linux/include/linux/ |
| H A D | pmu.h | 55 #define PMU_PWR_AC_PRESENT 0x00000001
58 #define PMU_BATT_PRESENT 0x00000001
59 #define PMU_BATT_CHARGING 0x00000002
60 #define PMU_BATT_TYPE_MASK 0x000000f0
61 #define PMU_BATT_TYPE_SMART 0x00000010 /* Smart battery */
62 #define PMU_BATT_TYPE_HOOPER 0x00000020 /* 3400/3500 */
63 #define PMU_BATT_TYPE_COMET 0x00000030 /* 2400 */
87 #define pmu_sys_suspended 0
|