1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 20ae797a8SArto Merilainen /* 30ae797a8SArto Merilainen * Copyright (c) 2015, NVIDIA Corporation. 40ae797a8SArto Merilainen */ 50ae797a8SArto Merilainen 60ae797a8SArto Merilainen #ifndef TEGRA_VIC_H 70ae797a8SArto Merilainen #define TEGRA_VIC_H 80ae797a8SArto Merilainen 90ae797a8SArto Merilainen /* VIC methods */ 100ae797a8SArto Merilainen 110ae797a8SArto Merilainen #define VIC_SET_FCE_UCODE_SIZE 0x0000071C 120ae797a8SArto Merilainen #define VIC_SET_FCE_UCODE_OFFSET 0x0000072C 130ae797a8SArto Merilainen 140ae797a8SArto Merilainen /* VIC registers */ 150ae797a8SArto Merilainen 16f3779cb1SThierry Reding #define VIC_THI_STREAMID0 0x00000030 17f3779cb1SThierry Reding #define VIC_THI_STREAMID1 0x00000034 18f3779cb1SThierry Reding 190ae797a8SArto Merilainen #define NV_PVIC_MISC_PRI_VIC_CG 0x000016d0 200ae797a8SArto Merilainen #define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0) 210ae797a8SArto Merilainen #define CG_IDLE_CG_EN (1 << 6) 220ae797a8SArto Merilainen #define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16) 230ae797a8SArto Merilainen 24f3779cb1SThierry Reding #define VIC_TFBIF_TRANSCFG 0x00002044 25f3779cb1SThierry Reding #define TRANSCFG_ATT(i, v) (((v) & 0x3) << (i * 4)) 26f3779cb1SThierry Reding #define TRANSCFG_SID_HW 0 27f3779cb1SThierry Reding #define TRANSCFG_SID_PHY 1 28f3779cb1SThierry Reding #define TRANSCFG_SID_FALCON 2 29f3779cb1SThierry Reding 300ae797a8SArto Merilainen /* Firmware offsets */ 310ae797a8SArto Merilainen 320ae797a8SArto Merilainen #define VIC_UCODE_FCE_HEADER_OFFSET (6*4) 330ae797a8SArto Merilainen #define VIC_UCODE_FCE_DATA_OFFSET (7*4) 340ae797a8SArto Merilainen #define FCE_UCODE_SIZE_OFFSET (2*4) 350ae797a8SArto Merilainen 360ae797a8SArto Merilainen #endif /* TEGRA_VIC_H */ 37