| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | mediatek,uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 - $ref: serial.yaml#
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
24 - items:
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| H A D | mtk-uart.txt | 1 * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible should contain:
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
[all …]
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| H A D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
[all …]
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| H A D | snps-dw-apb-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart
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| H A D | fsl-imx-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-im
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| H A D | samsung_uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Gre
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| H A D | amlogic,meson-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/amlogic,meson-uart
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| H A D | 8250.yaml | 3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter)
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
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| H A D | sirf-uart.txt | 4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
6 - reg : Offset and length of the register set for the device
7 - interrupts : Should contain uart interrupt
8 - fifosize : Should define hardware rx/tx fifo size
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
[all …]
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| H A D | omap_serial.txt | 1 OMAP UART controller
4 - compatible : should be "ti,am64-uart", "ti,am654-uart" for AM64 controllers
5 - compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
6 - compatible : should be "ti,am654-uart" for AM654 controllers
7 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
8 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
9 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
10 - compatible : should be "ti,am4372-uart" for AM437x controllers
11 - compatible : should be "ti,am3352-uart" for AM335x controllers
12 - compatible : should be "ti,dra742-uart" for DRA7x controllers
[all …]
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| H A D | sprd-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/sprd-uar
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| H A D | brcm,bcm7271-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
13 - $ref: serial.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
23 - enum:
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
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| H A D | ingenic,uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs UART controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: serial.yaml#
17 pattern: "^serial@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4740-uart
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| H A D | 8250_omap.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vignesh Raghavendra <vigneshr@ti.com>
13 - $ref: /schemas/serial/serial.yaml#
14 - $ref: /schemas/serial/rs485.yaml#
19 - enum:
20 - ti,am3352-uart
21 - ti,am4372-uart
22 - ti,am654-uart
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| H A D | fsl-imx-uart.txt | 1 * Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible : Should be "fsl,<soc>-uart"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
11 - fsl,inverted-tx , fsl,inverted-rx : Indicate that the hardware attached
15 - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
16 linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
17 you must enable either the "uart-has-rtscts" or the "rts-gpios"
18 properties. In case you use "uart-has-rtscts" the signal that controls
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| H A D | renesas,em-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/renesas,em-uar
[all...] |
| H A D | sifive-serial.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: serial.yaml#
20 - enum:
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| H A D | cdns,uart.txt | 1 Binding for Cadence UART Controller
4 - compatible :
5 Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
7 - reg: Should contain UART controller registers location and length.
8 - interrupts: Should contain UART controller interrupts.
9 - clocks: Must contain phandles to the UART clocks
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
12 See ../clocks/clock-bindings.txt for details.
[all …]
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| H A D | cirrus,clps711x-uart.txt | 1 * Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible: Should be "cirrus,ep7209-uart".
5 - reg: Address and length of the register set for the device.
6 - interrupts: Should contain UART TX and RX interrupt.
7 - clocks: Should contain UART core clock number.
8 - syscon: Phandle to SYSCON node, which contain UART control bits.
11 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
14 Note: Each UART port should have an alias correctly numbered
22 uart1: uart@80000480 {
23 compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart";
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | mediatek,uart-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek UART APDMA controller
10 - Long Cheng <long.cheng@mediatek.com>
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
17 - $ref: dma-controller.yaml#
22 - items:
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| /freebsd/share/man/man4/ |
| H A D | uart.4 | 1 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
32 .Nm uart
35 .Cd "device uart"
38 .Cd "device uart"
41 .Cd "device uart"
45 .Cd hint.uart.0.disabled="1"
46 .Cd hint.uart.0.baud="38400"
47 .Cd hint.uart.0.port="0x3f8"
48 .Cd hint.uart.0.flags="0x10"
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | pinctrl-mt7622.txt | 4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 "mediatek,mt7629-pinctrl" for MT7629 SoC
7 - reg: offset and length of the pinctrl space
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells: Should be two. The first cell is the pin number and the
14 - interrupt-controller : Marks the device node as an interrupt controller
16 If the property interrupt-controller is defined, following property is required
17 - reg-names: A string describing the "reg" entries. Must contain "eint".
18 - interrupts : The interrupt output from the controller.
[all …]
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| /freebsd/sys/dev/uart/ |
| H A D | uart_dev_msm.h | 1 /*-
31 ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos)))
33 /* UART Parity Mode */
41 /* UART Stop Bit Length */
49 /* UART Bits per Char */
57 /* 8-N-1 Configuration */
64 /* UART Operational Mode Registers (HSUART) */
79 /* UART Clock Selection Register, write only */
82 /* UART DM TX FIFO Registers - 4, write only */
85 /* UART Command Register, write only */
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/soc/aspeed/ |
| H A D | uart-routing.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/soc/aspeed/uart
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| /freebsd/bin/kenv/ |
| H A D | kenv.1 | 1 .\"-
122 Show kernel probe hints variable names and filter for the uart
124 .Bd -literal -offset indent
125 $ kenv -h -N | grep uart
126 hint.uart.0.at
127 hint.uart.0.flags
128 hint.uart.0.irq
129 hint.uart.0.port
130 hint.uart.1.at
131 hint.uart.1.irq
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