Lines Matching +full:- +full:uart
4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 "mediatek,mt7629-pinctrl" for MT7629 SoC
7 - reg: offset and length of the pinctrl space
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells: Should be two. The first cell is the pin number and the
14 - interrupt-controller : Marks the device node as an interrupt controller
16 If the property interrupt-controller is defined, following property is required
17 - reg-names: A string describing the "reg" entries. Must contain "eint".
18 - interrupts : The interrupt output from the controller.
19 - #interrupt-cells: Should be two.
21 Please refer to pinctrl-bindings.txt in this directory for details of the
29 parameters, such as pull-up, slew rate, etc.
40 The following generic properties as defined in pinctrl-bindings.txt are valid
44 - groups: An array of strings. Each string contains the name of a group.
46 - function: A string containing the name of the function to mux to the
51 The following generic properties as defined in pinctrl-bindings.txt are valid
55 - pins: An array of strings. Each string contains the name of a pin.
57 - groups: An array of strings. Each string contains the name of a group.
61 bias-disable, bias-pull, bias-pull-down, input-enable,
62 input-schmitt-enable, input-schmitt-disable, output-enable
63 output-low, output-high, drive-strength, slew-rate
65 Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for
67 Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA.
73 - mediatek,tdsel: An integer describing the steps for output level shifter duty
76 - mediatek,rdsel: An integer describing the steps for input level shifter duty
89 -----------------------------
196 "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
204 -------------------------------------------------------------------------
306 "uart0_0_tx_rx" "uart" 6, 7
307 "uart1_0_tx_rx" "uart" 55, 56
308 "uart1_0_rts_cts" "uart" 57, 58
309 "uart1_1_tx_rx" "uart" 73, 74
310 "uart1_1_rts_cts" "uart" 75, 76
311 "uart2_0_tx_rx" "uart" 3, 4
312 "uart2_0_rts_cts" "uart" 1, 2
313 "uart2_1_tx_rx" "uart" 51, 52
314 "uart2_1_rts_cts" "uart" 53, 54
315 "uart2_2_tx_rx" "uart" 59, 60
316 "uart2_2_rts_cts" "uart" 61, 62
317 "uart2_3_tx_rx" "uart" 95, 96
318 "uart3_0_tx_rx" "uart" 57, 58
319 "uart3_1_tx_rx" "uart" 81, 82
320 "uart3_1_rts_cts" "uart" 79, 80
321 "uart4_0_tx_rx" "uart" 61, 62
322 "uart4_1_tx_rx" "uart" 91, 92
323 "uart4_1_rts_cts" "uart" 93, 94
324 "uart4_2_tx_rx" "uart" 97, 98
325 "uart4_2_rts_cts" "uart" 95, 96
332 -----------------------------
414 "eth", "i2c", "led", "flash", "pcie", "pwm", "spi", "uart",
419 ----------------------------------------------------------------
443 "uart0_txd_rxd" "uart" 68, 69
444 "uart1_0_txd_rxd" "uart" 25, 26
445 "uart1_0_cts_rts" "uart" 27, 28
446 "uart1_1_txd_rxd" "uart" 53, 54
447 "uart1_1_cts_rts" "uart" 55, 56
448 "uart2_0_txd_rxd" "uart" 29, 30
449 "uart2_0_cts_rts" "uart" 31, 32
450 "uart2_1_txd_rxd" "uart" 57, 58
451 "uart2_1_cts_rts" "uart" 59, 60
461 compatible = "mediatek,mt7622-pinctrl";
463 gpio-controller;
464 #gpio-cells = <2>;
466 pinctrl_eth_default: eth-default {
467 mux-mdio {
470 drive-strength = <12>;
473 mux-gmac2 {
476 drive-strength = <12>;
479 mux-esw {
482 drive-strength = <8>;
485 conf-mdio {
487 bias-pull-up;