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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-mssr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
14 and MSSR (Module Standby and Software Reset) blocks are intimately connected,
18 - The CPG block generates various core clocks,
19 - The MSSR block provides two functions:
27 - renesas,r7s9210-cpg-mssr # RZ/A2
[all …]
/linux/arch/arm/mach-shmobile/
H A Dsetup-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 support
12 #include <linux/dma-map-ops.h>
23 #include "rcar-gen2.h"
26 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
27 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
28 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
29 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
30 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
31 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Drenesas,vsp1.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The VSP is a video processing engine that supports up-/down-scaling, alpha
15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
20 - enum:
21 - renesas,r9a07g044-vsp2 # RZ/G2L
22 - renesas,vsp1 # R-Car Gen2 and RZ/G1
23 - renesas,vsp2 # R-Car Gen3 and RZ/G2
[all …]
H A Drenesas,vin.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Video Input (VIN)
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 The R-Car Video Input (VIN) device provides video input capabilities for the
15 Renesas R-Car family of devices.
20 on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
25 - items:
26 - enum:
[all …]
H A Drenesas,drif.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
10 - Ramesh Shanmugasundaram <rashanmu@gmail.com>
11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
17 +---------------------+ +---------------------+
18 | |-----SCK------->|CLK |
19 | Master |-----SS-------->|SYNC DRIFn (slave) |
[all …]
H A Drenesas,jpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com>
20 - enum:
21 - renesas,jpu-r8a7790 # R-Car H2
22 - renesas,jpu-r8a7791 # R-Car M2-W
23 - renesas,jpu-r8a7792 # R-Car V2H
24 - renesas,jpu-r8a7793 # R-Car M2-N
25 - const: renesas,rcar-gen2-jpu # R-Car Gen2
[all …]
H A Drenesas,fdp1.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Fine Display Processor (FDP1)
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The FDP1 is a de-interlacing module which converts interlaced video to
21 - renesas,fdp1
32 power-domains:
42 Not allowed on R-Car Gen2, mandatory on R-Car Gen3.
45 - compatible
[all …]
/linux/drivers/clk/renesas/
H A Dr7s9210-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on r8a7795-cpg-mssr.c
13 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
16 #include "renesas-cpg-mssr.h"
169 parent = clks[core->parent]; in rza2_cpg_clk_register()
173 switch (core->id) { in rza2_cpg_clk_register()
185 return ERR_PTR(-EINVAL); in rza2_cpg_clk_register()
188 if (core->id == CLK_MAIN) in rza2_cpg_clk_register()
191 return clk_register_fixed_factor(NULL, core->name, in rza2_cpg_clk_register()
[all …]
H A Dr8a77970-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
7 * Based on r8a7795-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-cpg-lib.h"
22 #include "rcar-gen3-cpg.h"
125 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
[all …]
H A Dr8a779f0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a779a0-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen4-cpg.h"
152 DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
153 DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
167 DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
[all …]
H A Dr8a77995-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
136 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
137 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
138 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
139 DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
[all …]
H A Dr8a77980-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
129 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
130 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
139 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
140 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
[all …]
H A Drenesas-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Definitions of CPG Core Clocks
15 * - Clock outputs exported to DT
16 * - External input clocks
17 * - Internal CPG clocks
70 /* Convert from sparse base-100 to packed index space */
71 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
78 /* Convert from sparse base-10 to packed index space */
95 * SoC-specific CPG/MSSR Description
114 * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
[all …]
H A Dr8a774c0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a77990-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
149 DEF_MOD("sys-dmac2", 217, R8A774C0_CLK_S3D1),
150 DEF_MOD("sys-dmac1", 218, R8A774C0_CLK_S3D1),
151 DEF_MOD("sys-dmac0", 219, R8A774C0_CLK_S3D1),
162 DEF_MOD("usb3-if0", 328, R8A774C0_CLK_S3D1),
[all …]
H A Dr8a7791-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Glider bvba
7 * Based on clk-rcar-gen2.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen2-cpg.h"
96 DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
97 DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
98 DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
[all …]
H A Dr8a7743-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/soc/renesas/rcar-rst.h>
14 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
16 #include "renesas-cpg-mssr.h"
17 #include "rcar-gen2-cpg.h"
86 DEF_MOD("2d-dmac", 115, R8A7743_CLK_ZS),
87 DEF_MOD("fdp1-1", 118, R8A7743_CLK_ZS),
88 DEF_MOD("fdp1-0", 119, R8A7743_CLK_ZS),
104 DEF_MOD("sys-dmac1", 218, R8A7743_CLK_ZS),
105 DEF_MOD("sys-dmac0", 219, R8A7743_CLK_ZS),
[all …]
H A Dr8a779a0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
15 #include <linux/clk-provider.h>
20 #include <linux/soc/renesas/rcar-rst.h>
22 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
24 #include "renesas-cpg-mssr.h"
25 #include "rcar-gen4-cpg.h"
179 DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2),
185 DEF_MOD("sys-dmac1", 709, R8A779A0_CLK_S1D2),
186 DEF_MOD("sys-dmac2", 710, R8A779A0_CLK_S1D2),
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Drcar-gen3-thermal.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
5 $id: http://devicetree.org/schemas/thermal/rcar-gen3-thermal.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen3 Thermal Sensor
11 On most R-Car Gen3 and later SoCs, the thermal sensor controllers (TSC)
16 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
18 $ref: thermal-sensor.yaml#
23 - renesas,r8a774a1-thermal # RZ/G2M
24 - renesas,r8a774b1-thermal # RZ/G2N
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car LVDS Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14 Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
21 - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Drenesas,rcar-gen3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen3-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Generation 3 PCIe PHY
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
14 const: renesas,r8a77980-pcie-phy
22 power-domains:
28 '#phy-cells':
32 - compatible
[all …]
H A Drenesas,r8a779f0-ether-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,r8a779f0-ether-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 const: renesas,r8a779f0-ether-serdes
25 power-domains:
28 '#phy-cells':
33 - compatible
34 - reg
[all …]
/linux/include/dt-bindings/clock/
H A Dr7s9210-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/clock/renesas-cpg-mssr.h>
12 /* R7S9210 CPG Core Clocks */
H A Dr8a7795-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
10 /* r8a7795 CPG Core Clocks */
59 /* r8a7795 ES2.0 CPG Core Clocks */
H A Dr8a7792-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
11 /* r8a7792 CPG Core Clocks */
H A Dr8a77470-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
10 /* r8a77470 CPG Core Clocks */

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