14e591b89SThierry Bultel /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 24e591b89SThierry Bultel * 34e591b89SThierry Bultel * Copyright (C) 2025 Renesas Electronics Corp. 44e591b89SThierry Bultel */ 54e591b89SThierry Bultel 64e591b89SThierry Bultel #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ 74e591b89SThierry Bultel #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ 84e591b89SThierry Bultel 94e591b89SThierry Bultel #include <dt-bindings/clock/renesas-cpg-mssr.h> 104e591b89SThierry Bultel 114e591b89SThierry Bultel /* R9A09G077 CPG Core Clocks */ 124e591b89SThierry Bultel #define R9A09G077_CLK_CA55C0 0 134e591b89SThierry Bultel #define R9A09G077_CLK_CA55C1 1 144e591b89SThierry Bultel #define R9A09G077_CLK_CA55C2 2 154e591b89SThierry Bultel #define R9A09G077_CLK_CA55C3 3 164e591b89SThierry Bultel #define R9A09G077_CLK_CA55S 4 174e591b89SThierry Bultel #define R9A09G077_CLK_CR52_CPU0 5 184e591b89SThierry Bultel #define R9A09G077_CLK_CR52_CPU1 6 194e591b89SThierry Bultel #define R9A09G077_CLK_CKIO 7 204e591b89SThierry Bultel #define R9A09G077_CLK_PCLKAH 8 214e591b89SThierry Bultel #define R9A09G077_CLK_PCLKAM 9 224e591b89SThierry Bultel #define R9A09G077_CLK_PCLKAL 10 234e591b89SThierry Bultel #define R9A09G077_CLK_PCLKGPTL 11 244e591b89SThierry Bultel #define R9A09G077_CLK_PCLKH 12 254e591b89SThierry Bultel #define R9A09G077_CLK_PCLKM 13 2662ab7ac5SLad Prabhakar #define R9A09G077_CLK_PCLKL 14 272a76193fSLad Prabhakar #define R9A09G077_SDHI_CLKHS 15 288a5a0294SLad Prabhakar #define R9A09G077_USB_CLK 16 29*0dcfb6fcSLad Prabhakar #define R9A09G077_ETCLKA 17 30*0dcfb6fcSLad Prabhakar #define R9A09G077_ETCLKB 18 31*0dcfb6fcSLad Prabhakar #define R9A09G077_ETCLKC 19 32*0dcfb6fcSLad Prabhakar #define R9A09G077_ETCLKD 20 33*0dcfb6fcSLad Prabhakar #define R9A09G077_ETCLKE 21 344e591b89SThierry Bultel 354e591b89SThierry Bultel #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ 36