1*343e64a6SBiju Das /* SPDX-License-Identifier: GPL-2.0 2*343e64a6SBiju Das * 3*343e64a6SBiju Das * Copyright (C) 2018 Renesas Electronics Corp. 4*343e64a6SBiju Das */ 5*343e64a6SBiju Das #ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ 6*343e64a6SBiju Das #define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ 7*343e64a6SBiju Das 8*343e64a6SBiju Das #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*343e64a6SBiju Das 10*343e64a6SBiju Das /* r8a77470 CPG Core Clocks */ 11*343e64a6SBiju Das #define R8A77470_CLK_Z2 0 12*343e64a6SBiju Das #define R8A77470_CLK_ZTR 1 13*343e64a6SBiju Das #define R8A77470_CLK_ZTRD2 2 14*343e64a6SBiju Das #define R8A77470_CLK_ZT 3 15*343e64a6SBiju Das #define R8A77470_CLK_ZX 4 16*343e64a6SBiju Das #define R8A77470_CLK_ZS 5 17*343e64a6SBiju Das #define R8A77470_CLK_HP 6 18*343e64a6SBiju Das #define R8A77470_CLK_B 7 19*343e64a6SBiju Das #define R8A77470_CLK_LB 8 20*343e64a6SBiju Das #define R8A77470_CLK_P 9 21*343e64a6SBiju Das #define R8A77470_CLK_CL 10 22*343e64a6SBiju Das #define R8A77470_CLK_CP 11 23*343e64a6SBiju Das #define R8A77470_CLK_M2 12 24*343e64a6SBiju Das #define R8A77470_CLK_ZB3 13 25*343e64a6SBiju Das #define R8A77470_CLK_SDH 14 26*343e64a6SBiju Das #define R8A77470_CLK_SD0 15 27*343e64a6SBiju Das #define R8A77470_CLK_SD1 16 28*343e64a6SBiju Das #define R8A77470_CLK_SD2 17 29*343e64a6SBiju Das #define R8A77470_CLK_MP 18 30*343e64a6SBiju Das #define R8A77470_CLK_QSPI 19 31*343e64a6SBiju Das #define R8A77470_CLK_CPEX 20 32*343e64a6SBiju Das #define R8A77470_CLK_RCAN 21 33*343e64a6SBiju Das #define R8A77470_CLK_R 22 34*343e64a6SBiju Das #define R8A77470_CLK_OSC 23 35*343e64a6SBiju Das 36*343e64a6SBiju Das #endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */ 37