Merge tag 'v3.13-rc3' into drm-intel-next-queued

Linux 3.13-rc3

I need a backmerge for two reasons:
- For merging the ppgtt patches from Ben I need to pull in the bdw
support.
- We now have dupli

Merge tag 'v3.13-rc3' into drm-intel-next-queued

Linux 3.13-rc3

I need a backmerge for two reasons:
- For merging the ppgtt patches from Ben I need to pull in the bdw
support.
- We now have duplicated calls to intel_uncore_forcewake_reset in the
setup code to due 2 different patches merged into -next and 3.13.
The conflict is silen so I need the merge to be able to apply
Deepak's fixup patch.

Conflicts:
drivers/gpu/drm/i915/intel_display.c

Trivial conflict, it doesn't even show up in the merge diff.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Merge branch 'omap-for-v3.13/fixes-take4' into omap-for-v3.14/board-removal

Merge branch 'dt-regressions' into omap-for-v3.13/fixes-take4

Merge tag 'v3.13-rc1' into patchwork

Linux 3.13-rc1

* tag 'v3.13-rc1': (11465 commits)
Linux 3.13-rc1
ALSA: hda - Set current_headset_type to ALC_HEADSET_TYPE_ENUM (janitorial)
ALSA: hda - Pr

Merge tag 'v3.13-rc1' into patchwork

Linux 3.13-rc1

* tag 'v3.13-rc1': (11465 commits)
Linux 3.13-rc1
ALSA: hda - Set current_headset_type to ALC_HEADSET_TYPE_ENUM (janitorial)
ALSA: hda - Provide missing pin configs for VAIO with ALC260
mm: place page->pmd_huge_pte to right union
MAINTAINERS: add keyboard driver to Hyper-V file list
x86, mm: do not leak page->ptl for pmd page tables
ipc,shm: correct error return value in shmctl (SHM_UNLOCK)
mm, mempolicy: silence gcc warning
block/partitions/efi.c: fix bound check
ARM: drivers/rtc/rtc-at91rm9200.c: disable interrupts at shutdown
mm: hugetlbfs: fix hugetlbfs optimization
kernel: remove CONFIG_USE_GENERIC_SMP_HELPERS cleanly
ipc,shm: fix shm_file deletion races
mm: thp: give transparent hugepage code a separate copy_page
checkpatch: fix "Use of uninitialized value" warnings
configfs: fix race between dentry put and lookup
gso: handle new frag_list of frags GRO packets
GFS2: Fix ref count bug relating to atomic_open
genetlink: fix genl_set_err() group ID
genetlink: fix genlmsg_multicast() bug
...

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Merge tag 'v3.13-rc1' into asoc-arizona

Linux 3.13-rc1

Merge branch 'linus' into perf/urgent

Merge dependencies to apply a fix.

Signed-off-by: Ingo Molnar <mingo@kernel.org>

Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm

Pull ARM updates from Russell King:
"Included in this series are:

1. BE8 (modern big endian) changes for ARM from Ben Dooks

Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm

Pull ARM updates from Russell King:
"Included in this series are:

1. BE8 (modern big endian) changes for ARM from Ben Dooks
2. big.Little support from Nicolas Pitre and Dave Martin
3. support for LPAE systems with all system memory above 4GB
4. Perf updates from Will Deacon
5. Additional prefetching and other performance improvements from Will.
6. Neon-optimised AES implementation fro Ard.
7. A number of smaller fixes scattered around the place.

There is a rather horrid merge conflict in tools/perf - I was never
notified of the conflict because it originally occurred between Will's
tree and other stuff. Consequently I have a resolution which Will
forwarded me, which I'll forward on immediately after sending this
mail.

The other notable thing is I'm expecting some build breakage in the
crypto stuff on ARM only with Ard's AES patches. These were merged
into a stable git branch which others had already pulled, so there's
little I can do about this. The problem is caused because these
patches have a dependency on some code in the crypto git tree - I
tried requesting a branch I can pull to resolve these, and all I got
each time from the crypto people was "we'll revert our patches then"
which would only make things worse since I still don't have the
dependent patches. I've no idea what's going on there or how to
resolve that, and since I can't split these patches from the rest of
this pull request, I'm rather stuck with pushing this as-is or
reverting Ard's patches.

Since it should "come out in the wash" I've left them in - the only
build problems they seem to cause at the moment are with randconfigs,
and since it's a new feature anyway. However, if by -rc1 the
dependencies aren't in, I think it'd be best to revert Ard's patches"

I resolved the perf conflict roughly as per the patch sent by Russell,
but there may be some differences. Any errors are likely mine. Let's
see how the crypto issues work out..

* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (110 commits)
ARM: 7868/1: arm/arm64: remove atomic_clear_mask() in "include/asm/atomic.h"
ARM: 7867/1: include: asm: use 'int' instead of 'unsigned long' for 'oldval' in atomic_cmpxchg().
ARM: 7866/1: include: asm: use 'long long' instead of 'u64' within atomic.h
ARM: 7871/1: amba: Extend number of IRQS
ARM: 7887/1: Don't smp_cross_call() on UP devices in arch_irq_work_raise()
ARM: 7872/1: Support arch_irq_work_raise() via self IPIs
ARM: 7880/1: Clear the IT state independent of the Thumb-2 mode
ARM: 7878/1: nommu: Implement dummy early_paging_init()
ARM: 7876/1: clear Thumb-2 IT state on exception handling
ARM: 7874/2: bL_switcher: Remove cpu_hotplug_driver_{lock,unlock}()
ARM: footbridge: fix build warnings for netwinder
ARM: 7873/1: vfp: clear vfp_current_hw_state for dying cpu
ARM: fix misplaced arch_virt_to_idmap()
ARM: 7848/1: mcpm: Implement cpu_kill() to synchronise on powerdown
ARM: 7847/1: mcpm: Factor out logical-to-physical CPU translation
ARM: 7869/1: remove unused XSCALE_PMU Kconfig param
ARM: 7864/1: Handle 64-bit memory in case of 32-bit phys_addr_t
ARM: 7863/1: Let arm_add_memory() always use 64-bit arguments
ARM: 7862/1: pcpu: replace __get_cpu_var_uses
ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling code
...

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Merge branch 'devel-stable' into for-next

Conflicts:
arch/arm/include/asm/atomic.h
arch/arm/include/asm/hardirq.h
arch/arm/kernel/smp.c

ARM: 7874/2: bL_switcher: Remove cpu_hotplug_driver_{lock,unlock}()

Commit 6dedcca610c6 ("hotplug, powerpc, x86: Remove
cpu_hotplug_driver_lock())" removes the the definition of
cpu_hotplug_driver_{

ARM: 7874/2: bL_switcher: Remove cpu_hotplug_driver_{lock,unlock}()

Commit 6dedcca610c6 ("hotplug, powerpc, x86: Remove
cpu_hotplug_driver_lock())" removes the the definition of
cpu_hotplug_driver_{lock,unlock} APIs, thereby causing a build error.

Replace these calls with {lock,unlock}_device_hotplug().

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: bL_switcher: Add query interface to discover CPU affinities

When the switcher is active, there is no straightforward way to
figure out which logical CPU a given physical CPU maps to.

This patc

ARM: bL_switcher: Add query interface to discover CPU affinities

When the switcher is active, there is no straightforward way to
figure out which logical CPU a given physical CPU maps to.

This patch provides a function
bL_switcher_get_logical_index(mpidr), which is analogous to
get_logical_index().

This function returns the logical CPU on which the specified
physical CPU is grouped (or -EINVAL if unknown).
If the switcher is inactive or not present, -EUNATCH is returned instead.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>

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ARM: bL_switcher/trace: Add kernel trace trigger interface

This patch exports a bL_switcher_trace_trigger() function to
provide a means for drivers using the trace events to get the
current status w

ARM: bL_switcher/trace: Add kernel trace trigger interface

This patch exports a bL_switcher_trace_trigger() function to
provide a means for drivers using the trace events to get the
current status when starting a trace session.

Calling this function is equivalent to pinging the trace_trigger
file in sysfs.

Signed-off-by: Dave Martin <dave.martin@linaro.org>

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ARM: bL_switcher/trace: Add trace trigger for trace bootstrapping

When tracing switching, an external tracer needs a way to bootstrap
its knowledge of the logical<->physical CPU mapping.

This patch

ARM: bL_switcher/trace: Add trace trigger for trace bootstrapping

When tracing switching, an external tracer needs a way to bootstrap
its knowledge of the logical<->physical CPU mapping.

This patch adds a sysfs attribute trace_trigger. A write to this
attribute will generate a power:cpu_migrate_current event for each
online CPU, indicating the current physical CPU for each logical
CPU.

Activating or deactivating the switcher also generates these
events, so that the tracer knows about the resulting remapping of
affected CPUs.

Signed-off-by: Dave Martin <dave.martin@linaro.org>

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ARM: bL_switcher: Basic trace events support

This patch adds simple trace events to the b.L switcher code
to allow tracing of CPU migration events.

To make use of the trace events, you will need:

ARM: bL_switcher: Basic trace events support

This patch adds simple trace events to the b.L switcher code
to allow tracing of CPU migration events.

To make use of the trace events, you will need:

CONFIG_FTRACE=y
CONFIG_ENABLE_DEFAULT_TRACERS=y

The following events are added:
* power:cpu_migrate_begin
* power:cpu_migrate_finish

each with the following data:
u64 timestamp;
u32 cpu_hwid;

power:cpu_migrate_begin occurs immediately before the
switcher-specific migration operations start.
power:cpu_migrate_finish occurs immediately when migration is
completed.

The cpu_hwid field contains the ID fields of the MPIDR.

* For power:cpu_migrate_begin, cpu_hwid is the ID of the outbound
physical CPU (equivalent to (from_phys_cpu,from_phys_cluster)).

* For power:cpu_migrate_finish, cpu_hwid is the ID of the inbound
physical CPU (equivalent to (to_phys_cpu,to_phys_cluster)).

By design, the cpu_hwid field is masked in the same way as the
device tree cpu node reg property, allowing direct correlation to
the DT description of the hardware.

The timestamp is added in order to minimise timing noise. An
accurate system-wide clock should be used for generating this
(hopefully getnstimeofday is appropriate, but it could be changed).
It could be any monotonic shared clock, since the aim is to allow
accurate deltas to be computed. We don't necessarily care about
accurate synchronisation with wall clock time.

In practice, each switch takes place on a single logical CPU,
and the trace infrastructure should guarantee that events are
well-ordered with respect to a single logical CPU.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>

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ARM: bL_switcher: wait until inbound is alive before performing a switch

In some cases, a significant delay may be observed between the moment
a request for a CPU to come up is made and the moment i

ARM: bL_switcher: wait until inbound is alive before performing a switch

In some cases, a significant delay may be observed between the moment
a request for a CPU to come up is made and the moment it is ready to
start executing kernel code. This is especially true when a whole
cluster has to be powered up which may take in the order of miliseconds.
It is therefore a good idea to let the outbound CPU continue to execute
code in the mean time, and be notified when the inbound is ready before
performing the actual switch.

This is achieved by registering a completion block with the appropriate
IPI callback, and programming the sending of an IPI by the early assembly
code prior to entering the main kernel code. Once the IPI is delivered
to the outbound CPU, the completion block is "completed" and the switcher
thread is resumed.

Signed-off-by: Nicolas Pitre <nico@linaro.org>

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ARM: bL_switcher: synchronize the outbound with the inbound

Let's wait for the inbound CPU to come up and snoop some of the outbound
CPU cache before bringing the outbound CPU down. That should be

ARM: bL_switcher: synchronize the outbound with the inbound

Let's wait for the inbound CPU to come up and snoop some of the outbound
CPU cache before bringing the outbound CPU down. That should be more
efficient than going down right away.

Possible improvements might involve some monitoring of the CCI event
counters.

Signed-off-by: Nicolas Pitre <nico@linaro.org>

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ARM: bL_switcher: Add switch completion callback for bL_switch_request()

There is no explicit way to know when a switch started via
bL_switch_request() is complete. This can lead to unpredictable
b

ARM: bL_switcher: Add switch completion callback for bL_switch_request()

There is no explicit way to know when a switch started via
bL_switch_request() is complete. This can lead to unpredictable
behaviour when the switcher is controlled by a subsystem which
makes dynamic decisions (such as cpufreq).

The CPU PM notifier is not really suitable for signalling
completion, because the CPU could get suspended and resumed for
other, independent reasons while a switch request is in flight.
Adding a whole new notifier for this seems excessive, and may tempt
people to put heavyweight code on this path.

This patch implements a new bL_switch_request_cb() function that
allows for a per-request lightweight callback, private between the
switcher and the caller of bL_switch_request_cb().

Overlapping switches on a single CPU are considered incorrect if
they are requested via bL_switch_request_cb() with a callback (they
will lead to an unpredictable final state without explicit external
synchronisation to force the requests into a particular order).
Queuing requests robustly would be overkill because only one
subsystem should be attempting to control the switcher at any time.

Overlapping requests of this kind will be failed with -EBUSY to
indicate that the second request won't take effect and the
completer will never be called for it.

bL_switch_request() is retained as a wrapper round the new function,
with the old, fire-and-forget semantics. In this case the last request
will always win. The request may still be denied if a previous request
with a completer is still pending.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>

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ARM: bL_switcher: Add runtime control notifier

Some subsystems will need to respond synchronously to runtime
enabling and disabling of the switcher.

This patch adds a dedicated notifier interface t

ARM: bL_switcher: Add runtime control notifier

Some subsystems will need to respond synchronously to runtime
enabling and disabling of the switcher.

This patch adds a dedicated notifier interface to support such
subsystems. Pre- and post- enable/disable notifications are sent
to registered callbacks, allowing safe transition of non-b.L-
transparent subsystems across these control transitions.

Notifier callbacks may veto switcher (de)activation on pre notifications
only. Post notifications won't revert the action.

If enabling or disabling of the switcher fails after the pre-change
notification has been sent, subsystems which have registered
notifiers can be left in an inappropriate state.

This patch sends a suitable post-change notification on failure,
indicating that the old state has been reestablished.

For example, a failed initialisation will result in the following
sequence:

BL_NOTIFY_PRE_ENABLE
/* switcher initialisation fails */
BL_NOTIFY_POST_DISABLE

It is the responsibility of notified subsystems to respond in an
appropriate way.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>

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ARM: bL_switcher: Add synchronous enable/disable interface

Some subsystems will need to know for sure whether the switcher is
enabled or disabled during certain critical regions.

This patch provide

ARM: bL_switcher: Add synchronous enable/disable interface

Some subsystems will need to know for sure whether the switcher is
enabled or disabled during certain critical regions.

This patch provides a simple mutex-based mechanism to discover
whether the switcher is enabled and temporarily lock out further
enable/disable:

* bL_switcher_get_enabled() returns true iff the switcher is
enabled and temporarily inhibits enable/disable.

* bL_switcher_put_enabled() permits enable/disable of the switcher
again after a previous call to bL_switcher_get_enabled().

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>

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Merge branch 'iks_for_rmk' of git://git.linaro.org/people/nico/linux into devel-stable

Nicolas Pitre writes:

This is the first part of the patch series adding IKS (In-Kernel
Switcher) support for b

Merge branch 'iks_for_rmk' of git://git.linaro.org/people/nico/linux into devel-stable

Nicolas Pitre writes:

This is the first part of the patch series adding IKS (In-Kernel
Switcher) support for big.LITTLE system architectures. This consists of
the core patches only. Extra patches to come later will introduce
various optimizations and tracing support.

Those patches were posted on the list a while ago here:

http://news.gmane.org/group/gmane.linux.ports.arm.kernel/thread=253942

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ARM: bL_switcher: filter CPU hotplug requests when the switcher is active

Trying to support both the switcher and CPU hotplug at the same time
is tricky due to ambiguous semantics. So let's at leas

ARM: bL_switcher: filter CPU hotplug requests when the switcher is active

Trying to support both the switcher and CPU hotplug at the same time
is tricky due to ambiguous semantics. So let's at least prevent users
from messing around with those logical CPUs the switcher has removed
and those which were not active when the switcher was activated.

Signed-off-by: Nicolas Pitre <nico@linaro.org>

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ARM: bL_switcher: remove assumptions between logical and physical CPUs

Up to now, the logical CPU was somehow tied to the physical CPU number
within a cluster. This causes problems when forcing the

ARM: bL_switcher: remove assumptions between logical and physical CPUs

Up to now, the logical CPU was somehow tied to the physical CPU number
within a cluster. This causes problems when forcing the boot CPU to be
different from the first enumerated CPU in the device tree creating a
discrepancy between logical and physical CPU numbers.

Let's make the pairing completely independent from physical CPU numbers.

Let's keep only those logical CPUs with same initial CPU cluster to create
a uniform scheduler profile without having to modify any of the probed
topology and compute capacity data. This has the potential to create
a non contiguous CPU numbering space when the switcher is active with
potential impact on buggy user space tools. It is however better to fix
those tools rather than making the switcher code more intrusive.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

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ARM: bL_switcher: add kernel cmdline param to disable the switcher on boot

By adding no_bL_switcher to the kernel cmdline string, the switcher
won't be activated automatically at boot time. It is s

ARM: bL_switcher: add kernel cmdline param to disable the switcher on boot

By adding no_bL_switcher to the kernel cmdline string, the switcher
won't be activated automatically at boot time. It is still possible
to activate it later with:

echo 1 > /sys/kernel/bL_switcher/active

Signed-off-by: Nicolas Pitre <nico@linaro.org>

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ARM: bL_switcher: ability to enable and disable the switcher via sysfs

The /sys/kernel/bL_switcher/enable file allows to enable or disable
the switcher by writing 1 or 0 to it respectively. It is s

ARM: bL_switcher: ability to enable and disable the switcher via sysfs

The /sys/kernel/bL_switcher/enable file allows to enable or disable
the switcher by writing 1 or 0 to it respectively. It is still enabled
by default on boot.

Signed-off-by: Nicolas Pitre <nico@linaro.org>

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ARM: bL_switcher: do not hardcode GIC IDs in the code

Currently, GIC IDs are hardcoded making the code dependent on the 4+4 b.L
configuration. Let's allow for GIC IDs to be discovered upon switcher

ARM: bL_switcher: do not hardcode GIC IDs in the code

Currently, GIC IDs are hardcoded making the code dependent on the 4+4 b.L
configuration. Let's allow for GIC IDs to be discovered upon switcher
initialization to support other b.L configurations such as the 1+1 one,
or 2+3 as on the VExpress TC2.

Signed-off-by: Nicolas Pitre <nico@linaro.org>

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ARM: bL_switcher: hot-unplug half of the available CPUs

In a regular kernel configuration, all the CPUs are initially available.
But the switcher execution model uses half of them at any time. Inst

ARM: bL_switcher: hot-unplug half of the available CPUs

In a regular kernel configuration, all the CPUs are initially available.
But the switcher execution model uses half of them at any time. Instead
of hacking the DTB to remove half of the CPUs, let's remove them at
run time and make sure we still have a working switcher configuration.
This way, the same DTB can be used whether or not the switcher is used.

Signed-off-by: Nicolas Pitre <nico@linaro.org>

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