1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BCM6345 39 bool "BCM6345 Reset Controller" 40 depends on BMIPS_GENERIC || COMPILE_TEST 41 default BMIPS_GENERIC 42 help 43 This enables the reset controller driver for BCM6345 SoCs. 44 45config RESET_BERLIN 46 tristate "Berlin Reset Driver" 47 depends on ARCH_BERLIN || COMPILE_TEST 48 default m if ARCH_BERLIN 49 help 50 This enables the reset controller driver for Marvell Berlin SoCs. 51 52config RESET_BRCMSTB 53 tristate "Broadcom STB reset controller" 54 depends on ARCH_BRCMSTB || COMPILE_TEST 55 default ARCH_BRCMSTB 56 help 57 This enables the reset controller driver for Broadcom STB SoCs using 58 a SUN_TOP_CTRL_SW_INIT style controller. 59 60config RESET_BRCMSTB_RESCAL 61 tristate "Broadcom STB RESCAL reset controller" 62 depends on HAS_IOMEM 63 depends on ARCH_BRCMSTB || COMPILE_TEST 64 default ARCH_BRCMSTB 65 help 66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 67 BCM7216. 68 69config RESET_EYEQ 70 bool "Mobileye EyeQ reset controller" 71 depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST 72 select AUXILIARY_BUS 73 default MACH_EYEQ5 || MACH_EYEQ6H 74 help 75 This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L 76 and EyeQ6H SoCs. 77 78 It has one or more domains, with a varying number of resets in each. 79 Registers are located in a shared register region called OLB. EyeQ6H 80 has multiple reset instances. 81 82config RESET_GPIO 83 tristate "GPIO reset controller" 84 depends on GPIOLIB 85 help 86 This enables a generic reset controller for resets attached via 87 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 88 property. 89 90 If compiled as module, it will be called reset-gpio. 91 92config RESET_HSDK 93 bool "Synopsys HSDK Reset Driver" 94 depends on HAS_IOMEM 95 depends on ARC_SOC_HSDK || COMPILE_TEST 96 help 97 This enables the reset controller driver for HSDK board. 98 99config RESET_IMX7 100 tristate "i.MX7/8 Reset Driver" 101 depends on HAS_IOMEM 102 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 103 default y if SOC_IMX7D 104 select MFD_SYSCON 105 help 106 This enables the reset controller driver for i.MX7 SoCs. 107 108config RESET_IMX8MP_AUDIOMIX 109 tristate "i.MX8MP AudioMix Reset Driver" 110 depends on ARCH_MXC || COMPILE_TEST 111 select AUXILIARY_BUS 112 default CLK_IMX8MP 113 help 114 This enables the reset controller driver for i.MX8MP AudioMix 115 116config RESET_INTEL_GW 117 bool "Intel Reset Controller Driver" 118 depends on X86 || COMPILE_TEST 119 depends on OF && HAS_IOMEM 120 select REGMAP_MMIO 121 help 122 This enables the reset controller driver for Intel Gateway SoCs. 123 Say Y to control the reset signals provided by reset controller. 124 Otherwise, say N. 125 126config RESET_K210 127 bool "Reset controller driver for Canaan Kendryte K210 SoC" 128 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 129 select MFD_SYSCON 130 default SOC_CANAAN_K210 131 help 132 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 133 Say Y if you want to control reset signals provided by this 134 controller. 135 136config RESET_LANTIQ 137 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 138 default SOC_TYPE_XWAY 139 help 140 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 141 142config RESET_LPC18XX 143 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 144 default ARCH_LPC18XX 145 help 146 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 147 148config RESET_MCHP_SPARX5 149 bool "Microchip Sparx5 reset driver" 150 depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST 151 default y if SPARX5_SWITCH 152 select MFD_SYSCON 153 help 154 This driver supports switch core reset for the Microchip Sparx5 SoC. 155 156config RESET_MESON 157 tristate "Meson Reset Driver" 158 depends on ARCH_MESON || COMPILE_TEST 159 default ARCH_MESON 160 help 161 This enables the reset driver for Amlogic Meson SoCs. 162 163config RESET_MESON_AUDIO_ARB 164 tristate "Meson Audio Memory Arbiter Reset Driver" 165 depends on ARCH_MESON || COMPILE_TEST 166 help 167 This enables the reset driver for Audio Memory Arbiter of 168 Amlogic's A113 based SoCs 169 170config RESET_NPCM 171 bool "NPCM BMC Reset Driver" if COMPILE_TEST 172 default ARCH_NPCM 173 help 174 This enables the reset controller driver for Nuvoton NPCM 175 BMC SoCs. 176 177config RESET_NUVOTON_MA35D1 178 bool "Nuvoton MA35D1 Reset Driver" 179 depends on ARCH_MA35 || COMPILE_TEST 180 default ARCH_MA35 181 help 182 This enables the reset controller driver for Nuvoton MA35D1 SoC. 183 184config RESET_PISTACHIO 185 bool "Pistachio Reset Driver" 186 depends on MIPS || COMPILE_TEST 187 help 188 This enables the reset driver for ImgTec Pistachio SoCs. 189 190config RESET_POLARFIRE_SOC 191 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 192 depends on MCHP_CLK_MPFS 193 select AUXILIARY_BUS 194 default MCHP_CLK_MPFS 195 help 196 This driver supports peripheral reset for the Microchip PolarFire SoC 197 198config RESET_QCOM_AOSS 199 tristate "Qcom AOSS Reset Driver" 200 depends on ARCH_QCOM || COMPILE_TEST 201 help 202 This enables the AOSS (always on subsystem) reset driver 203 for Qualcomm SDM845 SoCs. Say Y if you want to control 204 reset signals provided by AOSS for Modem, Venus, ADSP, 205 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 206 207config RESET_QCOM_PDC 208 tristate "Qualcomm PDC Reset Driver" 209 depends on ARCH_QCOM || COMPILE_TEST 210 help 211 This enables the PDC (Power Domain Controller) reset driver 212 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 213 to control reset signals provided by PDC for Modem, Compute, 214 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 215 216config RESET_RASPBERRYPI 217 tristate "Raspberry Pi 4 Firmware Reset Driver" 218 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 219 default USB_XHCI_PCI 220 help 221 Raspberry Pi 4's co-processor controls some of the board's HW 222 initialization process, but it's up to Linux to trigger it when 223 relevant. This driver provides a reset controller capable of 224 interfacing with RPi4's co-processor and model these firmware 225 initialization routines as reset lines. 226 227config RESET_RZG2L_USBPHY_CTRL 228 tristate "Renesas RZ/G2L USBPHY control driver" 229 depends on ARCH_RZG2L || COMPILE_TEST 230 help 231 Support for USBPHY Control found on RZ/G2L family. It mainly 232 controls reset and power down of the USB/PHY. 233 234config RESET_SCMI 235 tristate "Reset driver controlled via ARM SCMI interface" 236 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 237 default ARM_SCMI_PROTOCOL 238 help 239 This driver provides support for reset signal/domains that are 240 controlled by firmware that implements the SCMI interface. 241 242 This driver uses SCMI Message Protocol to interact with the 243 firmware controlling all the reset signals. 244 245config RESET_SIMPLE 246 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 247 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 248 depends on HAS_IOMEM 249 help 250 This enables a simple reset controller driver for reset lines that 251 that can be asserted and deasserted by toggling bits in a contiguous, 252 exclusive register space. 253 254 Currently this driver supports: 255 - Altera SoCFPGAs 256 - ASPEED BMC SoCs 257 - Bitmain BM1880 SoC 258 - Realtek SoCs 259 - RCC reset controller in STM32 MCUs 260 - Allwinner SoCs 261 - SiFive FU740 SoCs 262 - Sophgo SoCs 263 264config RESET_SOCFPGA 265 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 266 default ARM && ARCH_INTEL_SOCFPGA 267 select RESET_SIMPLE 268 help 269 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 270 driver gets initialized early during platform init calls. 271 272config RESET_SUNPLUS 273 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 274 default ARCH_SUNPLUS 275 help 276 This enables the reset driver support for Sunplus SoCs. 277 The reset lines that can be asserted and deasserted by toggling bits 278 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 279 which means each register holds 16 reset lines. 280 281config RESET_SUNXI 282 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 283 default ARCH_SUNXI 284 select RESET_SIMPLE 285 help 286 This enables the reset driver for Allwinner SoCs. 287 288config RESET_TI_SCI 289 tristate "TI System Control Interface (TI-SCI) reset driver" 290 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 291 help 292 This enables the reset driver support over TI System Control Interface 293 available on some new TI's SoCs. If you wish to use reset resources 294 managed by the TI System Controller, say Y here. Otherwise, say N. 295 296config RESET_TI_SYSCON 297 tristate "TI SYSCON Reset Driver" 298 depends on HAS_IOMEM 299 select MFD_SYSCON 300 help 301 This enables the reset driver support for TI devices with 302 memory-mapped reset registers as part of a syscon device node. If 303 you wish to use the reset framework for such memory-mapped devices, 304 say Y here. Otherwise, say N. 305 306config RESET_TI_TPS380X 307 tristate "TI TPS380x Reset Driver" 308 select GPIOLIB 309 help 310 This enables the reset driver support for TI TPS380x devices. If 311 you wish to use the reset framework for such devices, say Y here. 312 Otherwise, say N. 313 314config RESET_TN48M_CPLD 315 tristate "Delta Networks TN48M switch CPLD reset controller" 316 depends on MFD_TN48M_CPLD || COMPILE_TEST 317 default MFD_TN48M_CPLD 318 help 319 This enables the reset controller driver for the Delta TN48M CPLD. 320 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 321 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 322 Microchip PD69200 PoE PSE controller. 323 324 This driver can also be built as a module. If so, the module will be 325 called reset-tn48m. 326 327config RESET_UNIPHIER 328 tristate "Reset controller driver for UniPhier SoCs" 329 depends on ARCH_UNIPHIER || COMPILE_TEST 330 depends on OF && MFD_SYSCON 331 default ARCH_UNIPHIER 332 help 333 Support for reset controllers on UniPhier SoCs. 334 Say Y if you want to control reset signals provided by System Control 335 block, Media I/O block, Peripheral Block. 336 337config RESET_UNIPHIER_GLUE 338 tristate "Reset driver in glue layer for UniPhier SoCs" 339 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 340 default ARCH_UNIPHIER 341 select RESET_SIMPLE 342 help 343 Support for peripheral core reset included in its own glue layer 344 on UniPhier SoCs. Say Y if you want to control reset signals 345 provided by the glue layer. 346 347config RESET_ZYNQ 348 bool "ZYNQ Reset Driver" if COMPILE_TEST 349 default ARCH_ZYNQ 350 help 351 This enables the reset controller driver for Xilinx Zynq SoCs. 352 353config RESET_ZYNQMP 354 bool "ZYNQMP Reset Driver" if COMPILE_TEST 355 default ARCH_ZYNQMP 356 help 357 This enables the reset controller driver for Xilinx ZynqMP SoCs. 358 359source "drivers/reset/starfive/Kconfig" 360source "drivers/reset/sti/Kconfig" 361source "drivers/reset/hisilicon/Kconfig" 362source "drivers/reset/tegra/Kconfig" 363 364endif 365