1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BCM6345 39 bool "BCM6345 Reset Controller" 40 depends on BMIPS_GENERIC || COMPILE_TEST 41 default BMIPS_GENERIC 42 help 43 This enables the reset controller driver for BCM6345 SoCs. 44 45config RESET_BERLIN 46 tristate "Berlin Reset Driver" 47 depends on ARCH_BERLIN || COMPILE_TEST 48 default m if ARCH_BERLIN 49 help 50 This enables the reset controller driver for Marvell Berlin SoCs. 51 52config RESET_BRCMSTB 53 tristate "Broadcom STB reset controller" 54 depends on ARCH_BRCMSTB || COMPILE_TEST 55 default ARCH_BRCMSTB 56 help 57 This enables the reset controller driver for Broadcom STB SoCs using 58 a SUN_TOP_CTRL_SW_INIT style controller. 59 60config RESET_BRCMSTB_RESCAL 61 tristate "Broadcom STB RESCAL reset controller" 62 depends on HAS_IOMEM 63 depends on ARCH_BRCMSTB || COMPILE_TEST 64 default ARCH_BRCMSTB 65 help 66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 67 BCM7216. 68 69config RESET_GPIO 70 tristate "GPIO reset controller" 71 help 72 This enables a generic reset controller for resets attached via 73 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 74 property. 75 76 If compiled as module, it will be called reset-gpio. 77 78config RESET_HSDK 79 bool "Synopsys HSDK Reset Driver" 80 depends on HAS_IOMEM 81 depends on ARC_SOC_HSDK || COMPILE_TEST 82 help 83 This enables the reset controller driver for HSDK board. 84 85config RESET_IMX7 86 tristate "i.MX7/8 Reset Driver" 87 depends on HAS_IOMEM 88 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 89 default y if SOC_IMX7D 90 select MFD_SYSCON 91 help 92 This enables the reset controller driver for i.MX7 SoCs. 93 94config RESET_INTEL_GW 95 bool "Intel Reset Controller Driver" 96 depends on X86 || COMPILE_TEST 97 depends on OF && HAS_IOMEM 98 select REGMAP_MMIO 99 help 100 This enables the reset controller driver for Intel Gateway SoCs. 101 Say Y to control the reset signals provided by reset controller. 102 Otherwise, say N. 103 104config RESET_K210 105 bool "Reset controller driver for Canaan Kendryte K210 SoC" 106 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 107 select MFD_SYSCON 108 default SOC_CANAAN_K210 109 help 110 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 111 Say Y if you want to control reset signals provided by this 112 controller. 113 114config RESET_LANTIQ 115 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 116 default SOC_TYPE_XWAY 117 help 118 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 119 120config RESET_LPC18XX 121 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 122 default ARCH_LPC18XX 123 help 124 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 125 126config RESET_MCHP_SPARX5 127 bool "Microchip Sparx5 reset driver" 128 depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST 129 default y if SPARX5_SWITCH 130 select MFD_SYSCON 131 help 132 This driver supports switch core reset for the Microchip Sparx5 SoC. 133 134config RESET_MESON 135 tristate "Meson Reset Driver" 136 depends on ARCH_MESON || COMPILE_TEST 137 default ARCH_MESON 138 help 139 This enables the reset driver for Amlogic Meson SoCs. 140 141config RESET_MESON_AUDIO_ARB 142 tristate "Meson Audio Memory Arbiter Reset Driver" 143 depends on ARCH_MESON || COMPILE_TEST 144 help 145 This enables the reset driver for Audio Memory Arbiter of 146 Amlogic's A113 based SoCs 147 148config RESET_NPCM 149 bool "NPCM BMC Reset Driver" if COMPILE_TEST 150 default ARCH_NPCM 151 help 152 This enables the reset controller driver for Nuvoton NPCM 153 BMC SoCs. 154 155config RESET_NUVOTON_MA35D1 156 bool "Nuvoton MA35D1 Reset Driver" 157 depends on ARCH_MA35 || COMPILE_TEST 158 default ARCH_MA35 159 help 160 This enables the reset controller driver for Nuvoton MA35D1 SoC. 161 162config RESET_PISTACHIO 163 bool "Pistachio Reset Driver" 164 depends on MIPS || COMPILE_TEST 165 help 166 This enables the reset driver for ImgTec Pistachio SoCs. 167 168config RESET_POLARFIRE_SOC 169 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 170 depends on MCHP_CLK_MPFS 171 select AUXILIARY_BUS 172 default MCHP_CLK_MPFS 173 help 174 This driver supports peripheral reset for the Microchip PolarFire SoC 175 176config RESET_QCOM_AOSS 177 tristate "Qcom AOSS Reset Driver" 178 depends on ARCH_QCOM || COMPILE_TEST 179 help 180 This enables the AOSS (always on subsystem) reset driver 181 for Qualcomm SDM845 SoCs. Say Y if you want to control 182 reset signals provided by AOSS for Modem, Venus, ADSP, 183 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 184 185config RESET_QCOM_PDC 186 tristate "Qualcomm PDC Reset Driver" 187 depends on ARCH_QCOM || COMPILE_TEST 188 help 189 This enables the PDC (Power Domain Controller) reset driver 190 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 191 to control reset signals provided by PDC for Modem, Compute, 192 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 193 194config RESET_RASPBERRYPI 195 tristate "Raspberry Pi 4 Firmware Reset Driver" 196 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 197 default USB_XHCI_PCI 198 help 199 Raspberry Pi 4's co-processor controls some of the board's HW 200 initialization process, but it's up to Linux to trigger it when 201 relevant. This driver provides a reset controller capable of 202 interfacing with RPi4's co-processor and model these firmware 203 initialization routines as reset lines. 204 205config RESET_RZG2L_USBPHY_CTRL 206 tristate "Renesas RZ/G2L USBPHY control driver" 207 depends on ARCH_RZG2L || COMPILE_TEST 208 help 209 Support for USBPHY Control found on RZ/G2L family. It mainly 210 controls reset and power down of the USB/PHY. 211 212config RESET_SCMI 213 tristate "Reset driver controlled via ARM SCMI interface" 214 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 215 default ARM_SCMI_PROTOCOL 216 help 217 This driver provides support for reset signal/domains that are 218 controlled by firmware that implements the SCMI interface. 219 220 This driver uses SCMI Message Protocol to interact with the 221 firmware controlling all the reset signals. 222 223config RESET_SIMPLE 224 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 225 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 226 depends on HAS_IOMEM 227 help 228 This enables a simple reset controller driver for reset lines that 229 that can be asserted and deasserted by toggling bits in a contiguous, 230 exclusive register space. 231 232 Currently this driver supports: 233 - Altera SoCFPGAs 234 - ASPEED BMC SoCs 235 - Bitmain BM1880 SoC 236 - Realtek SoCs 237 - RCC reset controller in STM32 MCUs 238 - Allwinner SoCs 239 - SiFive FU740 SoCs 240 - Sophgo SoCs 241 242config RESET_SOCFPGA 243 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 244 default ARM && ARCH_INTEL_SOCFPGA 245 select RESET_SIMPLE 246 help 247 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 248 driver gets initialized early during platform init calls. 249 250config RESET_SUNPLUS 251 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 252 default ARCH_SUNPLUS 253 help 254 This enables the reset driver support for Sunplus SoCs. 255 The reset lines that can be asserted and deasserted by toggling bits 256 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 257 which means each register holds 16 reset lines. 258 259config RESET_SUNXI 260 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 261 default ARCH_SUNXI 262 select RESET_SIMPLE 263 help 264 This enables the reset driver for Allwinner SoCs. 265 266config RESET_TI_SCI 267 tristate "TI System Control Interface (TI-SCI) reset driver" 268 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 269 help 270 This enables the reset driver support over TI System Control Interface 271 available on some new TI's SoCs. If you wish to use reset resources 272 managed by the TI System Controller, say Y here. Otherwise, say N. 273 274config RESET_TI_SYSCON 275 tristate "TI SYSCON Reset Driver" 276 depends on HAS_IOMEM 277 select MFD_SYSCON 278 help 279 This enables the reset driver support for TI devices with 280 memory-mapped reset registers as part of a syscon device node. If 281 you wish to use the reset framework for such memory-mapped devices, 282 say Y here. Otherwise, say N. 283 284config RESET_TI_TPS380X 285 tristate "TI TPS380x Reset Driver" 286 select GPIOLIB 287 help 288 This enables the reset driver support for TI TPS380x devices. If 289 you wish to use the reset framework for such devices, say Y here. 290 Otherwise, say N. 291 292config RESET_TN48M_CPLD 293 tristate "Delta Networks TN48M switch CPLD reset controller" 294 depends on MFD_TN48M_CPLD || COMPILE_TEST 295 default MFD_TN48M_CPLD 296 help 297 This enables the reset controller driver for the Delta TN48M CPLD. 298 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 299 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 300 Microchip PD69200 PoE PSE controller. 301 302 This driver can also be built as a module. If so, the module will be 303 called reset-tn48m. 304 305config RESET_UNIPHIER 306 tristate "Reset controller driver for UniPhier SoCs" 307 depends on ARCH_UNIPHIER || COMPILE_TEST 308 depends on OF && MFD_SYSCON 309 default ARCH_UNIPHIER 310 help 311 Support for reset controllers on UniPhier SoCs. 312 Say Y if you want to control reset signals provided by System Control 313 block, Media I/O block, Peripheral Block. 314 315config RESET_UNIPHIER_GLUE 316 tristate "Reset driver in glue layer for UniPhier SoCs" 317 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 318 default ARCH_UNIPHIER 319 select RESET_SIMPLE 320 help 321 Support for peripheral core reset included in its own glue layer 322 on UniPhier SoCs. Say Y if you want to control reset signals 323 provided by the glue layer. 324 325config RESET_ZYNQ 326 bool "ZYNQ Reset Driver" if COMPILE_TEST 327 default ARCH_ZYNQ 328 help 329 This enables the reset controller driver for Xilinx Zynq SoCs. 330 331source "drivers/reset/starfive/Kconfig" 332source "drivers/reset/sti/Kconfig" 333source "drivers/reset/hisilicon/Kconfig" 334source "drivers/reset/tegra/Kconfig" 335 336endif 337