1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ASPEED 26 tristate "ASPEED Reset Driver" 27 depends on ARCH_ASPEED || COMPILE_TEST 28 select AUXILIARY_BUS 29 help 30 This enables the reset controller driver for AST2700. 31 32config RESET_ATH79 33 bool "AR71xx Reset Driver" if COMPILE_TEST 34 default ATH79 35 help 36 This enables the ATH79 reset controller driver that supports the 37 AR71xx SoC reset controller. 38 39config RESET_AXS10X 40 bool "AXS10x Reset Driver" if COMPILE_TEST 41 default ARC_PLAT_AXS10X 42 help 43 This enables the reset controller driver for AXS10x. 44 45config RESET_BCM6345 46 bool "BCM6345 Reset Controller" 47 depends on BMIPS_GENERIC || COMPILE_TEST 48 default BMIPS_GENERIC 49 help 50 This enables the reset controller driver for BCM6345 SoCs. 51 52config RESET_BERLIN 53 tristate "Berlin Reset Driver" 54 depends on ARCH_BERLIN || COMPILE_TEST 55 default m if ARCH_BERLIN 56 help 57 This enables the reset controller driver for Marvell Berlin SoCs. 58 59config RESET_BRCMSTB 60 tristate "Broadcom STB reset controller" 61 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 62 default ARCH_BRCMSTB || ARCH_BCM2835 63 help 64 This enables the reset controller driver for Broadcom STB SoCs using 65 a SUN_TOP_CTRL_SW_INIT style controller. 66 67config RESET_BRCMSTB_RESCAL 68 tristate "Broadcom STB RESCAL reset controller" 69 depends on HAS_IOMEM 70 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 71 default ARCH_BRCMSTB || ARCH_BCM2835 72 help 73 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 74 BCM7216 or the BCM2712. 75 76config RESET_EIC7700 77 bool "Reset controller driver for ESWIN SoCs" 78 depends on ARCH_ESWIN || COMPILE_TEST 79 default ARCH_ESWIN 80 help 81 This enables the reset controller driver for ESWIN SoCs. This driver is 82 specific to ESWIN SoCs and should only be enabled if using such hardware. 83 The driver supports eic7700 series chips and provides functionality for 84 asserting and deasserting resets on the chip. 85 86config RESET_EYEQ 87 bool "Mobileye EyeQ reset controller" 88 depends on EYEQ || COMPILE_TEST 89 select AUXILIARY_BUS 90 default EYEQ 91 help 92 This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L 93 and EyeQ6H SoCs. 94 95 It has one or more domains, with a varying number of resets in each. 96 Registers are located in a shared register region called OLB. EyeQ6H 97 has multiple reset instances. 98 99config RESET_GPIO 100 tristate "GPIO reset controller" 101 depends on GPIOLIB 102 select AUXILIARY_BUS 103 help 104 This enables a generic reset controller for resets attached via 105 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 106 property. 107 108 If compiled as module, it will be called reset-gpio. 109 110config RESET_HSDK 111 bool "Synopsys HSDK Reset Driver" 112 depends on HAS_IOMEM 113 depends on ARC_SOC_HSDK || COMPILE_TEST 114 help 115 This enables the reset controller driver for HSDK board. 116 117config RESET_IMX_SCU 118 tristate "i.MX8Q Reset Driver" 119 depends on IMX_SCU && HAVE_ARM_SMCCC 120 depends on (ARM64 && ARCH_MXC) || COMPILE_TEST 121 help 122 This enables the reset controller driver for i.MX8QM/i.MX8QXP 123 124config RESET_IMX7 125 tristate "i.MX7/8 Reset Driver" 126 depends on HAS_IOMEM 127 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 128 default y if SOC_IMX7D 129 select MFD_SYSCON 130 help 131 This enables the reset controller driver for i.MX7 SoCs. 132 133config RESET_IMX8MP_AUDIOMIX 134 tristate "i.MX8MP AudioMix Reset Driver" 135 depends on ARCH_MXC || COMPILE_TEST 136 select AUXILIARY_BUS 137 default CLK_IMX8MP 138 help 139 This enables the reset controller driver for i.MX8MP AudioMix 140 141config RESET_INTEL_GW 142 bool "Intel Reset Controller Driver" 143 depends on X86 || COMPILE_TEST 144 depends on OF && HAS_IOMEM 145 select REGMAP_MMIO 146 help 147 This enables the reset controller driver for Intel Gateway SoCs. 148 Say Y to control the reset signals provided by reset controller. 149 Otherwise, say N. 150 151config RESET_K210 152 bool "Reset controller driver for Canaan Kendryte K210 SoC" 153 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 154 select MFD_SYSCON 155 default SOC_CANAAN_K210 156 help 157 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 158 Say Y if you want to control reset signals provided by this 159 controller. 160 161config RESET_K230 162 tristate "Reset controller driver for Canaan Kendryte K230 SoC" 163 depends on ARCH_CANAAN || COMPILE_TEST 164 default ARCH_CANAAN 165 help 166 Support for the Canaan Kendryte K230 RISC-V SoC reset controller. 167 Say Y if you want to control reset signals provided by this 168 controller. 169 170config RESET_LANTIQ 171 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 172 default SOC_TYPE_XWAY 173 help 174 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 175 176config RESET_LPC18XX 177 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 178 default ARCH_LPC18XX 179 help 180 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 181 182config RESET_MCHP_SPARX5 183 tristate "Microchip Sparx5 reset driver" 184 depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 185 default y if SPARX5_SWITCH 186 select MFD_SYSCON 187 help 188 This driver supports switch core reset for the Microchip Sparx5 SoC. 189 190config RESET_NPCM 191 bool "NPCM BMC Reset Driver" if COMPILE_TEST 192 default ARCH_NPCM 193 select AUXILIARY_BUS 194 help 195 This enables the reset controller driver for Nuvoton NPCM 196 BMC SoCs. 197 198config RESET_NUVOTON_MA35D1 199 bool "Nuvoton MA35D1 Reset Driver" 200 depends on ARCH_MA35 || COMPILE_TEST 201 default ARCH_MA35 202 help 203 This enables the reset controller driver for Nuvoton MA35D1 SoC. 204 205config RESET_PISTACHIO 206 bool "Pistachio Reset Driver" 207 depends on MIPS || COMPILE_TEST 208 help 209 This enables the reset driver for ImgTec Pistachio SoCs. 210 211config RESET_POLARFIRE_SOC 212 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 213 depends on MCHP_CLK_MPFS 214 depends on MFD_SYSCON 215 select AUXILIARY_BUS 216 default MCHP_CLK_MPFS 217 help 218 This driver supports peripheral reset for the Microchip PolarFire SoC 219 220config RESET_QCOM_AOSS 221 tristate "Qcom AOSS Reset Driver" 222 depends on ARCH_QCOM || COMPILE_TEST 223 help 224 This enables the AOSS (always on subsystem) reset driver 225 for Qualcomm SDM845 SoCs. Say Y if you want to control 226 reset signals provided by AOSS for Modem, Venus, ADSP, 227 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 228 229config RESET_QCOM_PDC 230 tristate "Qualcomm PDC Reset Driver" 231 depends on ARCH_QCOM || COMPILE_TEST 232 help 233 This enables the PDC (Power Domain Controller) reset driver 234 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 235 to control reset signals provided by PDC for Modem, Compute, 236 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 237 238config RESET_RASPBERRYPI 239 tristate "Raspberry Pi 4 Firmware Reset Driver" 240 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 241 default USB_XHCI_PCI 242 help 243 Raspberry Pi 4's co-processor controls some of the board's HW 244 initialization process, but it's up to Linux to trigger it when 245 relevant. This driver provides a reset controller capable of 246 interfacing with RPi4's co-processor and model these firmware 247 initialization routines as reset lines. 248 249config RESET_RZG2L_USBPHY_CTRL 250 tristate "Renesas RZ/G2L USBPHY control driver" 251 depends on ARCH_RZG2L || COMPILE_TEST 252 select MFD_SYSCON 253 help 254 Support for USBPHY Control found on RZ/G2L family. It mainly 255 controls reset and power down of the USB/PHY. 256 257config RESET_RZV2H_USB2PHY 258 tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" 259 depends on ARCH_RENESAS || COMPILE_TEST 260 select AUXILIARY_BUS 261 select REGMAP_MMIO 262 help 263 Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC 264 (and similar SoCs). 265 266config RESET_SCMI 267 tristate "Reset driver controlled via ARM SCMI interface" 268 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 269 default ARM_SCMI_PROTOCOL 270 help 271 This driver provides support for reset signal/domains that are 272 controlled by firmware that implements the SCMI interface. 273 274 This driver uses SCMI Message Protocol to interact with the 275 firmware controlling all the reset signals. 276 277config RESET_SIMPLE 278 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 279 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 280 depends on HAS_IOMEM 281 help 282 This enables a simple reset controller driver for reset lines that 283 that can be asserted and deasserted by toggling bits in a contiguous, 284 exclusive register space. 285 286 Currently this driver supports: 287 - Altera SoCFPGAs 288 - ASPEED BMC SoCs 289 - Bitmain BM1880 SoC 290 - Realtek SoCs 291 - RCC reset controller in STM32 MCUs 292 - Allwinner SoCs 293 - SiFive FU740 SoCs 294 - Sophgo SoCs 295 296config RESET_SKY1 297 bool "Cix Sky1 reset controller" 298 depends on ARCH_CIX || COMPILE_TEST 299 select REGMAP_MMIO 300 help 301 This enables the reset controller for Cix Sky1. 302 303config RESET_SKY1_AUDSS 304 tristate "Cix Sky1 Audio Subsystem reset controller" 305 depends on ARCH_CIX || COMPILE_TEST 306 select AUXILIARY_BUS 307 default CLK_SKY1_AUDSS 308 help 309 Support for block-level software reset lines in the Cix Sky1 310 Audio Subsystem (AUDSS) Clock and Reset Unit. Sixteen reset 311 outputs for audio peripherals are controlled through the CRU 312 register map. The driver binds as an auxiliary device from 313 the AUDSS clock driver. Say M or Y here if you want to build 314 this driver. 315 316config RESET_SOCFPGA 317 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 318 default ARM && ARCH_INTEL_SOCFPGA 319 select RESET_SIMPLE 320 help 321 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 322 driver gets initialized early during platform init calls. 323 324config RESET_SUNPLUS 325 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 326 default ARCH_SUNPLUS 327 help 328 This enables the reset driver support for Sunplus SoCs. 329 The reset lines that can be asserted and deasserted by toggling bits 330 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 331 which means each register holds 16 reset lines. 332 333config RESET_SUNXI 334 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 335 default ARCH_SUNXI 336 select RESET_SIMPLE 337 help 338 This enables the reset driver for Allwinner SoCs. 339 340config RESET_TENSTORRENT_ATLANTIS 341 tristate "Tenstorrent atlantis reset driver" 342 depends on ARCH_TENSTORRENT || COMPILE_TEST 343 select AUXILIARY_BUS 344 default ARCH_TENSTORRENT 345 help 346 This enables the driver for the reset controller 347 present in the Tenstorrent Atlantis SoC. 348 Enable this option to be able to use hardware 349 resets on Atalantis based systems. 350 351config RESET_TH1520 352 tristate "T-HEAD TH1520 reset controller" 353 depends on ARCH_THEAD || COMPILE_TEST 354 select REGMAP_MMIO 355 help 356 This driver provides support for the T-HEAD TH1520 SoC reset controller, 357 which manages hardware reset lines for SoC components such as the GPU. 358 Enable this option if you need to control hardware resets on TH1520-based 359 systems. 360 361config RESET_TI_SCI 362 tristate "TI System Control Interface (TI-SCI) reset driver" 363 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 364 help 365 This enables the reset driver support over TI System Control Interface 366 available on some new TI's SoCs. If you wish to use reset resources 367 managed by the TI System Controller, say Y here. Otherwise, say N. 368 369config RESET_TI_SYSCON 370 tristate "TI SYSCON Reset Driver" 371 depends on HAS_IOMEM 372 select MFD_SYSCON 373 help 374 This enables the reset driver support for TI devices with 375 memory-mapped reset registers as part of a syscon device node. If 376 you wish to use the reset framework for such memory-mapped devices, 377 say Y here. Otherwise, say N. 378 379config RESET_TI_TPS380X 380 tristate "TI TPS380x Reset Driver" 381 select GPIOLIB 382 help 383 This enables the reset driver support for TI TPS380x devices. If 384 you wish to use the reset framework for such devices, say Y here. 385 Otherwise, say N. 386 387config RESET_TN48M_CPLD 388 tristate "Delta Networks TN48M switch CPLD reset controller" 389 depends on MFD_TN48M_CPLD || COMPILE_TEST 390 default MFD_TN48M_CPLD 391 help 392 This enables the reset controller driver for the Delta TN48M CPLD. 393 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 394 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 395 Microchip PD69200 PoE PSE controller. 396 397 This driver can also be built as a module. If so, the module will be 398 called reset-tn48m. 399 400config RESET_UNIPHIER 401 tristate "Reset controller driver for UniPhier SoCs" 402 depends on ARCH_UNIPHIER || COMPILE_TEST 403 depends on OF && MFD_SYSCON 404 default ARCH_UNIPHIER 405 help 406 Support for reset controllers on UniPhier SoCs. 407 Say Y if you want to control reset signals provided by System Control 408 block, Media I/O block, Peripheral Block. 409 410config RESET_UNIPHIER_GLUE 411 tristate "Reset driver in glue layer for UniPhier SoCs" 412 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 413 default ARCH_UNIPHIER 414 select RESET_SIMPLE 415 help 416 Support for peripheral core reset included in its own glue layer 417 on UniPhier SoCs. Say Y if you want to control reset signals 418 provided by the glue layer. 419 420config RESET_ZYNQ 421 bool "ZYNQ Reset Driver" if COMPILE_TEST 422 default ARCH_ZYNQ 423 help 424 This enables the reset controller driver for Xilinx Zynq SoCs. 425 426config RESET_ZYNQMP 427 bool "ZYNQMP Reset Driver" if COMPILE_TEST 428 default ARCH_ZYNQMP 429 help 430 This enables the reset controller driver for Xilinx ZynqMP SoCs. 431 432source "drivers/reset/amlogic/Kconfig" 433source "drivers/reset/hisilicon/Kconfig" 434source "drivers/reset/spacemit/Kconfig" 435source "drivers/reset/starfive/Kconfig" 436source "drivers/reset/sti/Kconfig" 437source "drivers/reset/tegra/Kconfig" 438 439endif 440