1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ASPEED 26 tristate "ASPEED Reset Driver" 27 depends on ARCH_ASPEED || COMPILE_TEST 28 select AUXILIARY_BUS 29 help 30 This enables the reset controller driver for AST2700. 31 32config RESET_ATH79 33 bool "AR71xx Reset Driver" if COMPILE_TEST 34 default ATH79 35 help 36 This enables the ATH79 reset controller driver that supports the 37 AR71xx SoC reset controller. 38 39config RESET_AXS10X 40 bool "AXS10x Reset Driver" if COMPILE_TEST 41 default ARC_PLAT_AXS10X 42 help 43 This enables the reset controller driver for AXS10x. 44 45config RESET_BCM6345 46 bool "BCM6345 Reset Controller" 47 depends on BMIPS_GENERIC || COMPILE_TEST 48 default BMIPS_GENERIC 49 help 50 This enables the reset controller driver for BCM6345 SoCs. 51 52config RESET_BERLIN 53 tristate "Berlin Reset Driver" 54 depends on ARCH_BERLIN || COMPILE_TEST 55 default m if ARCH_BERLIN 56 help 57 This enables the reset controller driver for Marvell Berlin SoCs. 58 59config RESET_BRCMSTB 60 tristate "Broadcom STB reset controller" 61 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 62 default ARCH_BRCMSTB || ARCH_BCM2835 63 help 64 This enables the reset controller driver for Broadcom STB SoCs using 65 a SUN_TOP_CTRL_SW_INIT style controller. 66 67config RESET_BRCMSTB_RESCAL 68 tristate "Broadcom STB RESCAL reset controller" 69 depends on HAS_IOMEM 70 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 71 default ARCH_BRCMSTB || ARCH_BCM2835 72 help 73 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 74 BCM7216 or the BCM2712. 75 76config RESET_EYEQ 77 bool "Mobileye EyeQ reset controller" 78 depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST 79 select AUXILIARY_BUS 80 default MACH_EYEQ5 || MACH_EYEQ6H 81 help 82 This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L 83 and EyeQ6H SoCs. 84 85 It has one or more domains, with a varying number of resets in each. 86 Registers are located in a shared register region called OLB. EyeQ6H 87 has multiple reset instances. 88 89config RESET_GPIO 90 tristate "GPIO reset controller" 91 depends on GPIOLIB 92 help 93 This enables a generic reset controller for resets attached via 94 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 95 property. 96 97 If compiled as module, it will be called reset-gpio. 98 99config RESET_HSDK 100 bool "Synopsys HSDK Reset Driver" 101 depends on HAS_IOMEM 102 depends on ARC_SOC_HSDK || COMPILE_TEST 103 help 104 This enables the reset controller driver for HSDK board. 105 106config RESET_IMX_SCU 107 tristate "i.MX8Q Reset Driver" 108 depends on IMX_SCU && HAVE_ARM_SMCCC 109 depends on (ARM64 && ARCH_MXC) || COMPILE_TEST 110 help 111 This enables the reset controller driver for i.MX8QM/i.MX8QXP 112 113config RESET_IMX7 114 tristate "i.MX7/8 Reset Driver" 115 depends on HAS_IOMEM 116 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 117 default y if SOC_IMX7D 118 select MFD_SYSCON 119 help 120 This enables the reset controller driver for i.MX7 SoCs. 121 122config RESET_IMX8MP_AUDIOMIX 123 tristate "i.MX8MP AudioMix Reset Driver" 124 depends on ARCH_MXC || COMPILE_TEST 125 select AUXILIARY_BUS 126 default CLK_IMX8MP 127 help 128 This enables the reset controller driver for i.MX8MP AudioMix 129 130config RESET_INTEL_GW 131 bool "Intel Reset Controller Driver" 132 depends on X86 || COMPILE_TEST 133 depends on OF && HAS_IOMEM 134 select REGMAP_MMIO 135 help 136 This enables the reset controller driver for Intel Gateway SoCs. 137 Say Y to control the reset signals provided by reset controller. 138 Otherwise, say N. 139 140config RESET_K210 141 bool "Reset controller driver for Canaan Kendryte K210 SoC" 142 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 143 select MFD_SYSCON 144 default SOC_CANAAN_K210 145 help 146 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 147 Say Y if you want to control reset signals provided by this 148 controller. 149 150config RESET_K230 151 tristate "Reset controller driver for Canaan Kendryte K230 SoC" 152 depends on ARCH_CANAAN || COMPILE_TEST 153 depends on OF 154 help 155 Support for the Canaan Kendryte K230 RISC-V SoC reset controller. 156 Say Y if you want to control reset signals provided by this 157 controller. 158 159config RESET_LANTIQ 160 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 161 default SOC_TYPE_XWAY 162 help 163 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 164 165config RESET_LPC18XX 166 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 167 default ARCH_LPC18XX 168 help 169 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 170 171config RESET_MCHP_SPARX5 172 tristate "Microchip Sparx5 reset driver" 173 depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 174 default y if SPARX5_SWITCH 175 select MFD_SYSCON 176 help 177 This driver supports switch core reset for the Microchip Sparx5 SoC. 178 179config RESET_NPCM 180 bool "NPCM BMC Reset Driver" if COMPILE_TEST 181 default ARCH_NPCM 182 select AUXILIARY_BUS 183 help 184 This enables the reset controller driver for Nuvoton NPCM 185 BMC SoCs. 186 187config RESET_NUVOTON_MA35D1 188 bool "Nuvoton MA35D1 Reset Driver" 189 depends on ARCH_MA35 || COMPILE_TEST 190 default ARCH_MA35 191 help 192 This enables the reset controller driver for Nuvoton MA35D1 SoC. 193 194config RESET_PISTACHIO 195 bool "Pistachio Reset Driver" 196 depends on MIPS || COMPILE_TEST 197 help 198 This enables the reset driver for ImgTec Pistachio SoCs. 199 200config RESET_POLARFIRE_SOC 201 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 202 depends on MCHP_CLK_MPFS 203 depends on MFD_SYSCON 204 select AUXILIARY_BUS 205 default MCHP_CLK_MPFS 206 help 207 This driver supports peripheral reset for the Microchip PolarFire SoC 208 209config RESET_QCOM_AOSS 210 tristate "Qcom AOSS Reset Driver" 211 depends on ARCH_QCOM || COMPILE_TEST 212 help 213 This enables the AOSS (always on subsystem) reset driver 214 for Qualcomm SDM845 SoCs. Say Y if you want to control 215 reset signals provided by AOSS for Modem, Venus, ADSP, 216 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 217 218config RESET_QCOM_PDC 219 tristate "Qualcomm PDC Reset Driver" 220 depends on ARCH_QCOM || COMPILE_TEST 221 help 222 This enables the PDC (Power Domain Controller) reset driver 223 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 224 to control reset signals provided by PDC for Modem, Compute, 225 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 226 227config RESET_RASPBERRYPI 228 tristate "Raspberry Pi 4 Firmware Reset Driver" 229 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 230 default USB_XHCI_PCI 231 help 232 Raspberry Pi 4's co-processor controls some of the board's HW 233 initialization process, but it's up to Linux to trigger it when 234 relevant. This driver provides a reset controller capable of 235 interfacing with RPi4's co-processor and model these firmware 236 initialization routines as reset lines. 237 238config RESET_RZG2L_USBPHY_CTRL 239 tristate "Renesas RZ/G2L USBPHY control driver" 240 depends on ARCH_RZG2L || COMPILE_TEST 241 help 242 Support for USBPHY Control found on RZ/G2L family. It mainly 243 controls reset and power down of the USB/PHY. 244 245config RESET_RZV2H_USB2PHY 246 tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" 247 depends on ARCH_RENESAS || COMPILE_TEST 248 help 249 Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC 250 (and similar SoCs). 251 252config RESET_SCMI 253 tristate "Reset driver controlled via ARM SCMI interface" 254 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 255 default ARM_SCMI_PROTOCOL 256 help 257 This driver provides support for reset signal/domains that are 258 controlled by firmware that implements the SCMI interface. 259 260 This driver uses SCMI Message Protocol to interact with the 261 firmware controlling all the reset signals. 262 263config RESET_SIMPLE 264 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 265 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 266 depends on HAS_IOMEM 267 help 268 This enables a simple reset controller driver for reset lines that 269 that can be asserted and deasserted by toggling bits in a contiguous, 270 exclusive register space. 271 272 Currently this driver supports: 273 - Altera SoCFPGAs 274 - ASPEED BMC SoCs 275 - Bitmain BM1880 SoC 276 - Realtek SoCs 277 - RCC reset controller in STM32 MCUs 278 - Allwinner SoCs 279 - SiFive FU740 SoCs 280 - Sophgo SoCs 281 282config RESET_SOCFPGA 283 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 284 default ARM && ARCH_INTEL_SOCFPGA 285 select RESET_SIMPLE 286 help 287 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 288 driver gets initialized early during platform init calls. 289 290config RESET_SPACEMIT 291 tristate "SpacemiT reset driver" 292 depends on ARCH_SPACEMIT || COMPILE_TEST 293 select AUXILIARY_BUS 294 default ARCH_SPACEMIT 295 help 296 This enables the reset controller driver for SpacemiT SoCs, 297 including the K1. 298 299config RESET_SUNPLUS 300 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 301 default ARCH_SUNPLUS 302 help 303 This enables the reset driver support for Sunplus SoCs. 304 The reset lines that can be asserted and deasserted by toggling bits 305 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 306 which means each register holds 16 reset lines. 307 308config RESET_SUNXI 309 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 310 default ARCH_SUNXI 311 select RESET_SIMPLE 312 help 313 This enables the reset driver for Allwinner SoCs. 314 315config RESET_TH1520 316 tristate "T-HEAD TH1520 reset controller" 317 depends on ARCH_THEAD || COMPILE_TEST 318 select REGMAP_MMIO 319 help 320 This driver provides support for the T-HEAD TH1520 SoC reset controller, 321 which manages hardware reset lines for SoC components such as the GPU. 322 Enable this option if you need to control hardware resets on TH1520-based 323 systems. 324 325config RESET_TI_SCI 326 tristate "TI System Control Interface (TI-SCI) reset driver" 327 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 328 help 329 This enables the reset driver support over TI System Control Interface 330 available on some new TI's SoCs. If you wish to use reset resources 331 managed by the TI System Controller, say Y here. Otherwise, say N. 332 333config RESET_TI_SYSCON 334 tristate "TI SYSCON Reset Driver" 335 depends on HAS_IOMEM 336 select MFD_SYSCON 337 help 338 This enables the reset driver support for TI devices with 339 memory-mapped reset registers as part of a syscon device node. If 340 you wish to use the reset framework for such memory-mapped devices, 341 say Y here. Otherwise, say N. 342 343config RESET_TI_TPS380X 344 tristate "TI TPS380x Reset Driver" 345 select GPIOLIB 346 help 347 This enables the reset driver support for TI TPS380x devices. If 348 you wish to use the reset framework for such devices, say Y here. 349 Otherwise, say N. 350 351config RESET_TN48M_CPLD 352 tristate "Delta Networks TN48M switch CPLD reset controller" 353 depends on MFD_TN48M_CPLD || COMPILE_TEST 354 default MFD_TN48M_CPLD 355 help 356 This enables the reset controller driver for the Delta TN48M CPLD. 357 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 358 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 359 Microchip PD69200 PoE PSE controller. 360 361 This driver can also be built as a module. If so, the module will be 362 called reset-tn48m. 363 364config RESET_UNIPHIER 365 tristate "Reset controller driver for UniPhier SoCs" 366 depends on ARCH_UNIPHIER || COMPILE_TEST 367 depends on OF && MFD_SYSCON 368 default ARCH_UNIPHIER 369 help 370 Support for reset controllers on UniPhier SoCs. 371 Say Y if you want to control reset signals provided by System Control 372 block, Media I/O block, Peripheral Block. 373 374config RESET_UNIPHIER_GLUE 375 tristate "Reset driver in glue layer for UniPhier SoCs" 376 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 377 default ARCH_UNIPHIER 378 select RESET_SIMPLE 379 help 380 Support for peripheral core reset included in its own glue layer 381 on UniPhier SoCs. Say Y if you want to control reset signals 382 provided by the glue layer. 383 384config RESET_ZYNQ 385 bool "ZYNQ Reset Driver" if COMPILE_TEST 386 default ARCH_ZYNQ 387 help 388 This enables the reset controller driver for Xilinx Zynq SoCs. 389 390config RESET_ZYNQMP 391 bool "ZYNQMP Reset Driver" if COMPILE_TEST 392 default ARCH_ZYNQMP 393 help 394 This enables the reset controller driver for Xilinx ZynqMP SoCs. 395 396source "drivers/reset/amlogic/Kconfig" 397source "drivers/reset/starfive/Kconfig" 398source "drivers/reset/sti/Kconfig" 399source "drivers/reset/hisilicon/Kconfig" 400source "drivers/reset/tegra/Kconfig" 401 402endif 403