1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ASPEED 26 tristate "ASPEED Reset Driver" 27 depends on ARCH_ASPEED || COMPILE_TEST 28 select AUXILIARY_BUS 29 help 30 This enables the reset controller driver for AST2700. 31 32config RESET_ATH79 33 bool "AR71xx Reset Driver" if COMPILE_TEST 34 default ATH79 35 help 36 This enables the ATH79 reset controller driver that supports the 37 AR71xx SoC reset controller. 38 39config RESET_AXS10X 40 bool "AXS10x Reset Driver" if COMPILE_TEST 41 default ARC_PLAT_AXS10X 42 help 43 This enables the reset controller driver for AXS10x. 44 45config RESET_BCM6345 46 bool "BCM6345 Reset Controller" 47 depends on BMIPS_GENERIC || COMPILE_TEST 48 default BMIPS_GENERIC 49 help 50 This enables the reset controller driver for BCM6345 SoCs. 51 52config RESET_BERLIN 53 tristate "Berlin Reset Driver" 54 depends on ARCH_BERLIN || COMPILE_TEST 55 default m if ARCH_BERLIN 56 help 57 This enables the reset controller driver for Marvell Berlin SoCs. 58 59config RESET_BRCMSTB 60 tristate "Broadcom STB reset controller" 61 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 62 default ARCH_BRCMSTB || ARCH_BCM2835 63 help 64 This enables the reset controller driver for Broadcom STB SoCs using 65 a SUN_TOP_CTRL_SW_INIT style controller. 66 67config RESET_BRCMSTB_RESCAL 68 tristate "Broadcom STB RESCAL reset controller" 69 depends on HAS_IOMEM 70 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 71 default ARCH_BRCMSTB || ARCH_BCM2835 72 help 73 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 74 BCM7216 or the BCM2712. 75 76config RESET_EIC7700 77 bool "Reset controller driver for ESWIN SoCs" 78 depends on ARCH_ESWIN || COMPILE_TEST 79 default ARCH_ESWIN 80 help 81 This enables the reset controller driver for ESWIN SoCs. This driver is 82 specific to ESWIN SoCs and should only be enabled if using such hardware. 83 The driver supports eic7700 series chips and provides functionality for 84 asserting and deasserting resets on the chip. 85 86config RESET_EYEQ 87 bool "Mobileye EyeQ reset controller" 88 depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST 89 select AUXILIARY_BUS 90 default MACH_EYEQ5 || MACH_EYEQ6H 91 help 92 This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L 93 and EyeQ6H SoCs. 94 95 It has one or more domains, with a varying number of resets in each. 96 Registers are located in a shared register region called OLB. EyeQ6H 97 has multiple reset instances. 98 99config RESET_GPIO 100 tristate "GPIO reset controller" 101 depends on GPIOLIB 102 help 103 This enables a generic reset controller for resets attached via 104 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 105 property. 106 107 If compiled as module, it will be called reset-gpio. 108 109config RESET_HSDK 110 bool "Synopsys HSDK Reset Driver" 111 depends on HAS_IOMEM 112 depends on ARC_SOC_HSDK || COMPILE_TEST 113 help 114 This enables the reset controller driver for HSDK board. 115 116config RESET_IMX_SCU 117 tristate "i.MX8Q Reset Driver" 118 depends on IMX_SCU && HAVE_ARM_SMCCC 119 depends on (ARM64 && ARCH_MXC) || COMPILE_TEST 120 help 121 This enables the reset controller driver for i.MX8QM/i.MX8QXP 122 123config RESET_IMX7 124 tristate "i.MX7/8 Reset Driver" 125 depends on HAS_IOMEM 126 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 127 default y if SOC_IMX7D 128 select MFD_SYSCON 129 help 130 This enables the reset controller driver for i.MX7 SoCs. 131 132config RESET_IMX8MP_AUDIOMIX 133 tristate "i.MX8MP AudioMix Reset Driver" 134 depends on ARCH_MXC || COMPILE_TEST 135 select AUXILIARY_BUS 136 default CLK_IMX8MP 137 help 138 This enables the reset controller driver for i.MX8MP AudioMix 139 140config RESET_INTEL_GW 141 bool "Intel Reset Controller Driver" 142 depends on X86 || COMPILE_TEST 143 depends on OF && HAS_IOMEM 144 select REGMAP_MMIO 145 help 146 This enables the reset controller driver for Intel Gateway SoCs. 147 Say Y to control the reset signals provided by reset controller. 148 Otherwise, say N. 149 150config RESET_K210 151 bool "Reset controller driver for Canaan Kendryte K210 SoC" 152 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 153 select MFD_SYSCON 154 default SOC_CANAAN_K210 155 help 156 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 157 Say Y if you want to control reset signals provided by this 158 controller. 159 160config RESET_K230 161 tristate "Reset controller driver for Canaan Kendryte K230 SoC" 162 depends on ARCH_CANAAN || COMPILE_TEST 163 depends on OF 164 help 165 Support for the Canaan Kendryte K230 RISC-V SoC reset controller. 166 Say Y if you want to control reset signals provided by this 167 controller. 168 169config RESET_LANTIQ 170 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 171 default SOC_TYPE_XWAY 172 help 173 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 174 175config RESET_LPC18XX 176 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 177 default ARCH_LPC18XX 178 help 179 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 180 181config RESET_MCHP_SPARX5 182 tristate "Microchip Sparx5 reset driver" 183 depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 184 default y if SPARX5_SWITCH 185 select MFD_SYSCON 186 help 187 This driver supports switch core reset for the Microchip Sparx5 SoC. 188 189config RESET_NPCM 190 bool "NPCM BMC Reset Driver" if COMPILE_TEST 191 default ARCH_NPCM 192 select AUXILIARY_BUS 193 help 194 This enables the reset controller driver for Nuvoton NPCM 195 BMC SoCs. 196 197config RESET_NUVOTON_MA35D1 198 bool "Nuvoton MA35D1 Reset Driver" 199 depends on ARCH_MA35 || COMPILE_TEST 200 default ARCH_MA35 201 help 202 This enables the reset controller driver for Nuvoton MA35D1 SoC. 203 204config RESET_PISTACHIO 205 bool "Pistachio Reset Driver" 206 depends on MIPS || COMPILE_TEST 207 help 208 This enables the reset driver for ImgTec Pistachio SoCs. 209 210config RESET_POLARFIRE_SOC 211 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 212 depends on MCHP_CLK_MPFS 213 select AUXILIARY_BUS 214 default MCHP_CLK_MPFS 215 help 216 This driver supports peripheral reset for the Microchip PolarFire SoC 217 218config RESET_QCOM_AOSS 219 tristate "Qcom AOSS Reset Driver" 220 depends on ARCH_QCOM || COMPILE_TEST 221 help 222 This enables the AOSS (always on subsystem) reset driver 223 for Qualcomm SDM845 SoCs. Say Y if you want to control 224 reset signals provided by AOSS for Modem, Venus, ADSP, 225 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 226 227config RESET_QCOM_PDC 228 tristate "Qualcomm PDC Reset Driver" 229 depends on ARCH_QCOM || COMPILE_TEST 230 help 231 This enables the PDC (Power Domain Controller) reset driver 232 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 233 to control reset signals provided by PDC for Modem, Compute, 234 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 235 236config RESET_RASPBERRYPI 237 tristate "Raspberry Pi 4 Firmware Reset Driver" 238 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 239 default USB_XHCI_PCI 240 help 241 Raspberry Pi 4's co-processor controls some of the board's HW 242 initialization process, but it's up to Linux to trigger it when 243 relevant. This driver provides a reset controller capable of 244 interfacing with RPi4's co-processor and model these firmware 245 initialization routines as reset lines. 246 247config RESET_RZG2L_USBPHY_CTRL 248 tristate "Renesas RZ/G2L USBPHY control driver" 249 depends on ARCH_RZG2L || COMPILE_TEST 250 select MFD_SYSCON 251 help 252 Support for USBPHY Control found on RZ/G2L family. It mainly 253 controls reset and power down of the USB/PHY. 254 255config RESET_RZV2H_USB2PHY 256 tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" 257 depends on ARCH_RENESAS || COMPILE_TEST 258 help 259 Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC 260 (and similar SoCs). 261 262config RESET_SCMI 263 tristate "Reset driver controlled via ARM SCMI interface" 264 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 265 default ARM_SCMI_PROTOCOL 266 help 267 This driver provides support for reset signal/domains that are 268 controlled by firmware that implements the SCMI interface. 269 270 This driver uses SCMI Message Protocol to interact with the 271 firmware controlling all the reset signals. 272 273config RESET_SIMPLE 274 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 275 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 276 depends on HAS_IOMEM 277 help 278 This enables a simple reset controller driver for reset lines that 279 that can be asserted and deasserted by toggling bits in a contiguous, 280 exclusive register space. 281 282 Currently this driver supports: 283 - Altera SoCFPGAs 284 - ASPEED BMC SoCs 285 - Bitmain BM1880 SoC 286 - Realtek SoCs 287 - RCC reset controller in STM32 MCUs 288 - Allwinner SoCs 289 - SiFive FU740 SoCs 290 - Sophgo SoCs 291 292config RESET_SOCFPGA 293 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 294 default ARM && ARCH_INTEL_SOCFPGA 295 select RESET_SIMPLE 296 help 297 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 298 driver gets initialized early during platform init calls. 299 300config RESET_SPACEMIT 301 tristate "SpacemiT reset driver" 302 depends on ARCH_SPACEMIT || COMPILE_TEST 303 select AUXILIARY_BUS 304 default ARCH_SPACEMIT 305 help 306 This enables the reset controller driver for SpacemiT SoCs, 307 including the K1. 308 309config RESET_SUNPLUS 310 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 311 default ARCH_SUNPLUS 312 help 313 This enables the reset driver support for Sunplus SoCs. 314 The reset lines that can be asserted and deasserted by toggling bits 315 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 316 which means each register holds 16 reset lines. 317 318config RESET_SUNXI 319 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 320 default ARCH_SUNXI 321 select RESET_SIMPLE 322 help 323 This enables the reset driver for Allwinner SoCs. 324 325config RESET_TH1520 326 tristate "T-HEAD TH1520 reset controller" 327 depends on ARCH_THEAD || COMPILE_TEST 328 select REGMAP_MMIO 329 help 330 This driver provides support for the T-HEAD TH1520 SoC reset controller, 331 which manages hardware reset lines for SoC components such as the GPU. 332 Enable this option if you need to control hardware resets on TH1520-based 333 systems. 334 335config RESET_TI_SCI 336 tristate "TI System Control Interface (TI-SCI) reset driver" 337 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 338 help 339 This enables the reset driver support over TI System Control Interface 340 available on some new TI's SoCs. If you wish to use reset resources 341 managed by the TI System Controller, say Y here. Otherwise, say N. 342 343config RESET_TI_SYSCON 344 tristate "TI SYSCON Reset Driver" 345 depends on HAS_IOMEM 346 select MFD_SYSCON 347 help 348 This enables the reset driver support for TI devices with 349 memory-mapped reset registers as part of a syscon device node. If 350 you wish to use the reset framework for such memory-mapped devices, 351 say Y here. Otherwise, say N. 352 353config RESET_TI_TPS380X 354 tristate "TI TPS380x Reset Driver" 355 select GPIOLIB 356 help 357 This enables the reset driver support for TI TPS380x devices. If 358 you wish to use the reset framework for such devices, say Y here. 359 Otherwise, say N. 360 361config RESET_TN48M_CPLD 362 tristate "Delta Networks TN48M switch CPLD reset controller" 363 depends on MFD_TN48M_CPLD || COMPILE_TEST 364 default MFD_TN48M_CPLD 365 help 366 This enables the reset controller driver for the Delta TN48M CPLD. 367 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 368 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 369 Microchip PD69200 PoE PSE controller. 370 371 This driver can also be built as a module. If so, the module will be 372 called reset-tn48m. 373 374config RESET_UNIPHIER 375 tristate "Reset controller driver for UniPhier SoCs" 376 depends on ARCH_UNIPHIER || COMPILE_TEST 377 depends on OF && MFD_SYSCON 378 default ARCH_UNIPHIER 379 help 380 Support for reset controllers on UniPhier SoCs. 381 Say Y if you want to control reset signals provided by System Control 382 block, Media I/O block, Peripheral Block. 383 384config RESET_UNIPHIER_GLUE 385 tristate "Reset driver in glue layer for UniPhier SoCs" 386 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 387 default ARCH_UNIPHIER 388 select RESET_SIMPLE 389 help 390 Support for peripheral core reset included in its own glue layer 391 on UniPhier SoCs. Say Y if you want to control reset signals 392 provided by the glue layer. 393 394config RESET_ZYNQ 395 bool "ZYNQ Reset Driver" if COMPILE_TEST 396 default ARCH_ZYNQ 397 help 398 This enables the reset controller driver for Xilinx Zynq SoCs. 399 400config RESET_ZYNQMP 401 bool "ZYNQMP Reset Driver" if COMPILE_TEST 402 default ARCH_ZYNQMP 403 help 404 This enables the reset controller driver for Xilinx ZynqMP SoCs. 405 406source "drivers/reset/amlogic/Kconfig" 407source "drivers/reset/starfive/Kconfig" 408source "drivers/reset/sti/Kconfig" 409source "drivers/reset/hisilicon/Kconfig" 410source "drivers/reset/tegra/Kconfig" 411 412endif 413