1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BCM6345 39 bool "BCM6345 Reset Controller" 40 depends on BMIPS_GENERIC || COMPILE_TEST 41 default BMIPS_GENERIC 42 help 43 This enables the reset controller driver for BCM6345 SoCs. 44 45config RESET_BERLIN 46 bool "Berlin Reset Driver" if COMPILE_TEST 47 default ARCH_BERLIN 48 help 49 This enables the reset controller driver for Marvell Berlin SoCs. 50 51config RESET_BRCMSTB 52 tristate "Broadcom STB reset controller" 53 depends on ARCH_BRCMSTB || COMPILE_TEST 54 default ARCH_BRCMSTB 55 help 56 This enables the reset controller driver for Broadcom STB SoCs using 57 a SUN_TOP_CTRL_SW_INIT style controller. 58 59config RESET_BRCMSTB_RESCAL 60 bool "Broadcom STB RESCAL reset controller" 61 depends on HAS_IOMEM 62 default ARCH_BRCMSTB || COMPILE_TEST 63 help 64 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 65 BCM7216. 66 67config RESET_HSDK 68 bool "Synopsys HSDK Reset Driver" 69 depends on HAS_IOMEM 70 depends on ARC_SOC_HSDK || COMPILE_TEST 71 help 72 This enables the reset controller driver for HSDK board. 73 74config RESET_IMX7 75 tristate "i.MX7/8 Reset Driver" 76 depends on HAS_IOMEM 77 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 78 default y if SOC_IMX7D 79 select MFD_SYSCON 80 help 81 This enables the reset controller driver for i.MX7 SoCs. 82 83config RESET_INTEL_GW 84 bool "Intel Reset Controller Driver" 85 depends on OF && HAS_IOMEM 86 select REGMAP_MMIO 87 help 88 This enables the reset controller driver for Intel Gateway SoCs. 89 Say Y to control the reset signals provided by reset controller. 90 Otherwise, say N. 91 92config RESET_K210 93 bool "Reset controller driver for Canaan Kendryte K210 SoC" 94 depends on (SOC_CANAAN || COMPILE_TEST) && OF 95 select MFD_SYSCON 96 default SOC_CANAAN 97 help 98 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 99 Say Y if you want to control reset signals provided by this 100 controller. 101 102config RESET_LANTIQ 103 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 104 default SOC_TYPE_XWAY 105 help 106 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 107 108config RESET_LPC18XX 109 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 110 default ARCH_LPC18XX 111 help 112 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 113 114config RESET_MCHP_SPARX5 115 bool "Microchip Sparx5 reset driver" 116 depends on HAS_IOMEM || COMPILE_TEST 117 default y if SPARX5_SWITCH 118 select MFD_SYSCON 119 help 120 This driver supports switch core reset for the Microchip Sparx5 SoC. 121 122config RESET_MESON 123 tristate "Meson Reset Driver" 124 depends on ARCH_MESON || COMPILE_TEST 125 default ARCH_MESON 126 help 127 This enables the reset driver for Amlogic Meson SoCs. 128 129config RESET_MESON_AUDIO_ARB 130 tristate "Meson Audio Memory Arbiter Reset Driver" 131 depends on ARCH_MESON || COMPILE_TEST 132 help 133 This enables the reset driver for Audio Memory Arbiter of 134 Amlogic's A113 based SoCs 135 136config RESET_NPCM 137 bool "NPCM BMC Reset Driver" if COMPILE_TEST 138 default ARCH_NPCM 139 help 140 This enables the reset controller driver for Nuvoton NPCM 141 BMC SoCs. 142 143config RESET_OXNAS 144 bool 145 146config RESET_PISTACHIO 147 bool "Pistachio Reset Driver" if COMPILE_TEST 148 default MACH_PISTACHIO 149 help 150 This enables the reset driver for ImgTec Pistachio SoCs. 151 152config RESET_QCOM_AOSS 153 tristate "Qcom AOSS Reset Driver" 154 depends on ARCH_QCOM || COMPILE_TEST 155 help 156 This enables the AOSS (always on subsystem) reset driver 157 for Qualcomm SDM845 SoCs. Say Y if you want to control 158 reset signals provided by AOSS for Modem, Venus, ADSP, 159 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 160 161config RESET_QCOM_PDC 162 tristate "Qualcomm PDC Reset Driver" 163 depends on ARCH_QCOM || COMPILE_TEST 164 help 165 This enables the PDC (Power Domain Controller) reset driver 166 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 167 to control reset signals provided by PDC for Modem, Compute, 168 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 169 170config RESET_RASPBERRYPI 171 tristate "Raspberry Pi 4 Firmware Reset Driver" 172 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 173 default USB_XHCI_PCI 174 help 175 Raspberry Pi 4's co-processor controls some of the board's HW 176 initialization process, but it's up to Linux to trigger it when 177 relevant. This driver provides a reset controller capable of 178 interfacing with RPi4's co-processor and model these firmware 179 initialization routines as reset lines. 180 181config RESET_SCMI 182 tristate "Reset driver controlled via ARM SCMI interface" 183 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 184 default ARM_SCMI_PROTOCOL 185 help 186 This driver provides support for reset signal/domains that are 187 controlled by firmware that implements the SCMI interface. 188 189 This driver uses SCMI Message Protocol to interact with the 190 firmware controlling all the reset signals. 191 192config RESET_SIMPLE 193 bool "Simple Reset Controller Driver" if COMPILE_TEST 194 default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 195 help 196 This enables a simple reset controller driver for reset lines that 197 that can be asserted and deasserted by toggling bits in a contiguous, 198 exclusive register space. 199 200 Currently this driver supports: 201 - Altera SoCFPGAs 202 - ASPEED BMC SoCs 203 - Bitmain BM1880 SoC 204 - Realtek SoCs 205 - RCC reset controller in STM32 MCUs 206 - Allwinner SoCs 207 - ZTE's zx2967 family 208 - SiFive FU740 SoCs 209 210config RESET_STM32MP157 211 bool "STM32MP157 Reset Driver" if COMPILE_TEST 212 default MACH_STM32MP157 213 help 214 This enables the RCC reset controller driver for STM32 MPUs. 215 216config RESET_SOCFPGA 217 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 218 default ARM && ARCH_INTEL_SOCFPGA 219 select RESET_SIMPLE 220 help 221 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 222 driver gets initialized early during platform init calls. 223 224config RESET_SUNXI 225 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 226 default ARCH_SUNXI 227 select RESET_SIMPLE 228 help 229 This enables the reset driver for Allwinner SoCs. 230 231config RESET_TI_SCI 232 tristate "TI System Control Interface (TI-SCI) reset driver" 233 depends on TI_SCI_PROTOCOL 234 help 235 This enables the reset driver support over TI System Control Interface 236 available on some new TI's SoCs. If you wish to use reset resources 237 managed by the TI System Controller, say Y here. Otherwise, say N. 238 239config RESET_TI_SYSCON 240 tristate "TI SYSCON Reset Driver" 241 depends on HAS_IOMEM 242 select MFD_SYSCON 243 help 244 This enables the reset driver support for TI devices with 245 memory-mapped reset registers as part of a syscon device node. If 246 you wish to use the reset framework for such memory-mapped devices, 247 say Y here. Otherwise, say N. 248 249config RESET_UNIPHIER 250 tristate "Reset controller driver for UniPhier SoCs" 251 depends on ARCH_UNIPHIER || COMPILE_TEST 252 depends on OF && MFD_SYSCON 253 default ARCH_UNIPHIER 254 help 255 Support for reset controllers on UniPhier SoCs. 256 Say Y if you want to control reset signals provided by System Control 257 block, Media I/O block, Peripheral Block. 258 259config RESET_UNIPHIER_GLUE 260 tristate "Reset driver in glue layer for UniPhier SoCs" 261 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 262 default ARCH_UNIPHIER 263 select RESET_SIMPLE 264 help 265 Support for peripheral core reset included in its own glue layer 266 on UniPhier SoCs. Say Y if you want to control reset signals 267 provided by the glue layer. 268 269config RESET_ZYNQ 270 bool "ZYNQ Reset Driver" if COMPILE_TEST 271 default ARCH_ZYNQ 272 help 273 This enables the reset controller driver for Xilinx Zynq SoCs. 274 275source "drivers/reset/sti/Kconfig" 276source "drivers/reset/hisilicon/Kconfig" 277source "drivers/reset/tegra/Kconfig" 278 279endif 280