1config ARCH_HAS_RESET_CONTROLLER 2 bool 3 4menuconfig RESET_CONTROLLER 5 bool "Reset Controller Support" 6 default y if ARCH_HAS_RESET_CONTROLLER 7 help 8 Generic Reset Controller support. 9 10 This framework is designed to abstract reset handling of devices 11 via GPIOs or SoC-internal reset controller modules. 12 13 If unsure, say no. 14 15if RESET_CONTROLLER 16 17config RESET_A10SR 18 tristate "Altera Arria10 System Resource Reset" 19 depends on MFD_ALTERA_A10SR 20 help 21 This option enables support for the external reset functions for 22 peripheral PHYs on the Altera Arria10 System Resource Chip. 23 24config RESET_ATH79 25 bool "AR71xx Reset Driver" if COMPILE_TEST 26 default ATH79 27 help 28 This enables the ATH79 reset controller driver that supports the 29 AR71xx SoC reset controller. 30 31config RESET_AXS10X 32 bool "AXS10x Reset Driver" if COMPILE_TEST 33 default ARC_PLAT_AXS10X 34 help 35 This enables the reset controller driver for AXS10x. 36 37config RESET_BERLIN 38 bool "Berlin Reset Driver" if COMPILE_TEST 39 default ARCH_BERLIN 40 help 41 This enables the reset controller driver for Marvell Berlin SoCs. 42 43config RESET_HSDK 44 bool "Synopsys HSDK Reset Driver" 45 depends on HAS_IOMEM 46 depends on ARC_SOC_HSDK || COMPILE_TEST 47 help 48 This enables the reset controller driver for HSDK board. 49 50config RESET_IMX7 51 bool "i.MX7 Reset Driver" if COMPILE_TEST 52 depends on HAS_IOMEM 53 default SOC_IMX7D 54 select MFD_SYSCON 55 help 56 This enables the reset controller driver for i.MX7 SoCs. 57 58config RESET_LANTIQ 59 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 60 default SOC_TYPE_XWAY 61 help 62 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 63 64config RESET_LPC18XX 65 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 66 default ARCH_LPC18XX 67 help 68 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 69 70config RESET_MESON 71 bool "Meson Reset Driver" if COMPILE_TEST 72 default ARCH_MESON 73 help 74 This enables the reset driver for Amlogic Meson SoCs. 75 76config RESET_MESON_AUDIO_ARB 77 tristate "Meson Audio Memory Arbiter Reset Driver" 78 depends on ARCH_MESON || COMPILE_TEST 79 help 80 This enables the reset driver for Audio Memory Arbiter of 81 Amlogic's A113 based SoCs 82 83config RESET_OXNAS 84 bool 85 86config RESET_PISTACHIO 87 bool "Pistachio Reset Driver" if COMPILE_TEST 88 default MACH_PISTACHIO 89 help 90 This enables the reset driver for ImgTec Pistachio SoCs. 91 92config RESET_QCOM_AOSS 93 bool "Qcom AOSS Reset Driver" 94 depends on ARCH_QCOM || COMPILE_TEST 95 help 96 This enables the AOSS (always on subsystem) reset driver 97 for Qualcomm SDM845 SoCs. Say Y if you want to control 98 reset signals provided by AOSS for Modem, Venus, ADSP, 99 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 100 101config RESET_QCOM_PDC 102 tristate "Qualcomm PDC Reset Driver" 103 depends on ARCH_QCOM || COMPILE_TEST 104 help 105 This enables the PDC (Power Domain Controller) reset driver 106 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 107 to control reset signals provided by PDC for Modem, Compute, 108 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 109 110config RESET_SIMPLE 111 bool "Simple Reset Controller Driver" if COMPILE_TEST 112 default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED 113 help 114 This enables a simple reset controller driver for reset lines that 115 that can be asserted and deasserted by toggling bits in a contiguous, 116 exclusive register space. 117 118 Currently this driver supports: 119 - Altera SoCFPGAs 120 - ASPEED BMC SoCs 121 - RCC reset controller in STM32 MCUs 122 - Allwinner SoCs 123 - ZTE's zx2967 family 124 125config RESET_STM32MP157 126 bool "STM32MP157 Reset Driver" if COMPILE_TEST 127 default MACH_STM32MP157 128 help 129 This enables the RCC reset controller driver for STM32 MPUs. 130 131config RESET_SOCFPGA 132 bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA 133 default ARCH_SOCFPGA 134 select RESET_SIMPLE 135 help 136 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 137 driver gets initialized early during platform init calls. 138 139config RESET_SUNXI 140 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 141 default ARCH_SUNXI 142 select RESET_SIMPLE 143 help 144 This enables the reset driver for Allwinner SoCs. 145 146config RESET_TI_SCI 147 tristate "TI System Control Interface (TI-SCI) reset driver" 148 depends on TI_SCI_PROTOCOL 149 help 150 This enables the reset driver support over TI System Control Interface 151 available on some new TI's SoCs. If you wish to use reset resources 152 managed by the TI System Controller, say Y here. Otherwise, say N. 153 154config RESET_TI_SYSCON 155 tristate "TI SYSCON Reset Driver" 156 depends on HAS_IOMEM 157 select MFD_SYSCON 158 help 159 This enables the reset driver support for TI devices with 160 memory-mapped reset registers as part of a syscon device node. If 161 you wish to use the reset framework for such memory-mapped devices, 162 say Y here. Otherwise, say N. 163 164config RESET_UNIPHIER 165 tristate "Reset controller driver for UniPhier SoCs" 166 depends on ARCH_UNIPHIER || COMPILE_TEST 167 depends on OF && MFD_SYSCON 168 default ARCH_UNIPHIER 169 help 170 Support for reset controllers on UniPhier SoCs. 171 Say Y if you want to control reset signals provided by System Control 172 block, Media I/O block, Peripheral Block. 173 174config RESET_UNIPHIER_GLUE 175 tristate "Reset driver in glue layer for UniPhier SoCs" 176 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 177 default ARCH_UNIPHIER 178 select RESET_SIMPLE 179 help 180 Support for peripheral core reset included in its own glue layer 181 on UniPhier SoCs. Say Y if you want to control reset signals 182 provided by the glue layer. 183 184config RESET_ZYNQ 185 bool "ZYNQ Reset Driver" if COMPILE_TEST 186 default ARCH_ZYNQ 187 help 188 This enables the reset controller driver for Xilinx Zynq SoCs. 189 190source "drivers/reset/sti/Kconfig" 191source "drivers/reset/hisilicon/Kconfig" 192source "drivers/reset/tegra/Kconfig" 193 194endif 195