1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ASPEED 26 tristate "ASPEED Reset Driver" 27 depends on ARCH_ASPEED || COMPILE_TEST 28 select AUXILIARY_BUS 29 help 30 This enables the reset controller driver for AST2700. 31 32config RESET_ATH79 33 bool "AR71xx Reset Driver" if COMPILE_TEST 34 default ATH79 35 help 36 This enables the ATH79 reset controller driver that supports the 37 AR71xx SoC reset controller. 38 39config RESET_AXS10X 40 bool "AXS10x Reset Driver" if COMPILE_TEST 41 default ARC_PLAT_AXS10X 42 help 43 This enables the reset controller driver for AXS10x. 44 45config RESET_BCM6345 46 bool "BCM6345 Reset Controller" 47 depends on BMIPS_GENERIC || COMPILE_TEST 48 default BMIPS_GENERIC 49 help 50 This enables the reset controller driver for BCM6345 SoCs. 51 52config RESET_BERLIN 53 tristate "Berlin Reset Driver" 54 depends on ARCH_BERLIN || COMPILE_TEST 55 default m if ARCH_BERLIN 56 help 57 This enables the reset controller driver for Marvell Berlin SoCs. 58 59config RESET_BRCMSTB 60 tristate "Broadcom STB reset controller" 61 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 62 default ARCH_BRCMSTB || ARCH_BCM2835 63 help 64 This enables the reset controller driver for Broadcom STB SoCs using 65 a SUN_TOP_CTRL_SW_INIT style controller. 66 67config RESET_BRCMSTB_RESCAL 68 tristate "Broadcom STB RESCAL reset controller" 69 depends on HAS_IOMEM 70 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 71 default ARCH_BRCMSTB || ARCH_BCM2835 72 help 73 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 74 BCM7216 or the BCM2712. 75 76config RESET_EIC7700 77 bool "Reset controller driver for ESWIN SoCs" 78 depends on ARCH_ESWIN || COMPILE_TEST 79 default ARCH_ESWIN 80 help 81 This enables the reset controller driver for ESWIN SoCs. This driver is 82 specific to ESWIN SoCs and should only be enabled if using such hardware. 83 The driver supports eic7700 series chips and provides functionality for 84 asserting and deasserting resets on the chip. 85 86config RESET_EYEQ 87 bool "Mobileye EyeQ reset controller" 88 depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST 89 select AUXILIARY_BUS 90 default MACH_EYEQ5 || MACH_EYEQ6H 91 help 92 This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L 93 and EyeQ6H SoCs. 94 95 It has one or more domains, with a varying number of resets in each. 96 Registers are located in a shared register region called OLB. EyeQ6H 97 has multiple reset instances. 98 99config RESET_GPIO 100 tristate "GPIO reset controller" 101 depends on GPIOLIB 102 select AUXILIARY_BUS 103 help 104 This enables a generic reset controller for resets attached via 105 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 106 property. 107 108 If compiled as module, it will be called reset-gpio. 109 110config RESET_HSDK 111 bool "Synopsys HSDK Reset Driver" 112 depends on HAS_IOMEM 113 depends on ARC_SOC_HSDK || COMPILE_TEST 114 help 115 This enables the reset controller driver for HSDK board. 116 117config RESET_IMX_SCU 118 tristate "i.MX8Q Reset Driver" 119 depends on IMX_SCU && HAVE_ARM_SMCCC 120 depends on (ARM64 && ARCH_MXC) || COMPILE_TEST 121 help 122 This enables the reset controller driver for i.MX8QM/i.MX8QXP 123 124config RESET_IMX7 125 tristate "i.MX7/8 Reset Driver" 126 depends on HAS_IOMEM 127 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 128 default y if SOC_IMX7D 129 select MFD_SYSCON 130 help 131 This enables the reset controller driver for i.MX7 SoCs. 132 133config RESET_IMX8MP_AUDIOMIX 134 tristate "i.MX8MP AudioMix Reset Driver" 135 depends on ARCH_MXC || COMPILE_TEST 136 select AUXILIARY_BUS 137 default CLK_IMX8MP 138 help 139 This enables the reset controller driver for i.MX8MP AudioMix 140 141config RESET_INTEL_GW 142 bool "Intel Reset Controller Driver" 143 depends on X86 || COMPILE_TEST 144 depends on OF && HAS_IOMEM 145 select REGMAP_MMIO 146 help 147 This enables the reset controller driver for Intel Gateway SoCs. 148 Say Y to control the reset signals provided by reset controller. 149 Otherwise, say N. 150 151config RESET_K210 152 bool "Reset controller driver for Canaan Kendryte K210 SoC" 153 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 154 select MFD_SYSCON 155 default SOC_CANAAN_K210 156 help 157 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 158 Say Y if you want to control reset signals provided by this 159 controller. 160 161config RESET_K230 162 tristate "Reset controller driver for Canaan Kendryte K230 SoC" 163 depends on ARCH_CANAAN || COMPILE_TEST 164 depends on OF 165 help 166 Support for the Canaan Kendryte K230 RISC-V SoC reset controller. 167 Say Y if you want to control reset signals provided by this 168 controller. 169 170config RESET_LANTIQ 171 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 172 default SOC_TYPE_XWAY 173 help 174 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 175 176config RESET_LPC18XX 177 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 178 default ARCH_LPC18XX 179 help 180 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 181 182config RESET_MCHP_SPARX5 183 tristate "Microchip Sparx5 reset driver" 184 depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 185 default y if SPARX5_SWITCH 186 select MFD_SYSCON 187 help 188 This driver supports switch core reset for the Microchip Sparx5 SoC. 189 190config RESET_NPCM 191 bool "NPCM BMC Reset Driver" if COMPILE_TEST 192 default ARCH_NPCM 193 select AUXILIARY_BUS 194 help 195 This enables the reset controller driver for Nuvoton NPCM 196 BMC SoCs. 197 198config RESET_NUVOTON_MA35D1 199 bool "Nuvoton MA35D1 Reset Driver" 200 depends on ARCH_MA35 || COMPILE_TEST 201 default ARCH_MA35 202 help 203 This enables the reset controller driver for Nuvoton MA35D1 SoC. 204 205config RESET_PISTACHIO 206 bool "Pistachio Reset Driver" 207 depends on MIPS || COMPILE_TEST 208 help 209 This enables the reset driver for ImgTec Pistachio SoCs. 210 211config RESET_POLARFIRE_SOC 212 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 213 depends on MCHP_CLK_MPFS 214 select AUXILIARY_BUS 215 default MCHP_CLK_MPFS 216 help 217 This driver supports peripheral reset for the Microchip PolarFire SoC 218 219config RESET_QCOM_AOSS 220 tristate "Qcom AOSS Reset Driver" 221 depends on ARCH_QCOM || COMPILE_TEST 222 help 223 This enables the AOSS (always on subsystem) reset driver 224 for Qualcomm SDM845 SoCs. Say Y if you want to control 225 reset signals provided by AOSS for Modem, Venus, ADSP, 226 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 227 228config RESET_QCOM_PDC 229 tristate "Qualcomm PDC Reset Driver" 230 depends on ARCH_QCOM || COMPILE_TEST 231 help 232 This enables the PDC (Power Domain Controller) reset driver 233 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 234 to control reset signals provided by PDC for Modem, Compute, 235 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 236 237config RESET_RASPBERRYPI 238 tristate "Raspberry Pi 4 Firmware Reset Driver" 239 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 240 default USB_XHCI_PCI 241 help 242 Raspberry Pi 4's co-processor controls some of the board's HW 243 initialization process, but it's up to Linux to trigger it when 244 relevant. This driver provides a reset controller capable of 245 interfacing with RPi4's co-processor and model these firmware 246 initialization routines as reset lines. 247 248config RESET_RZG2L_USBPHY_CTRL 249 tristate "Renesas RZ/G2L USBPHY control driver" 250 depends on ARCH_RZG2L || COMPILE_TEST 251 select MFD_SYSCON 252 help 253 Support for USBPHY Control found on RZ/G2L family. It mainly 254 controls reset and power down of the USB/PHY. 255 256config RESET_RZV2H_USB2PHY 257 tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" 258 depends on ARCH_RENESAS || COMPILE_TEST 259 help 260 Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC 261 (and similar SoCs). 262 263config RESET_SCMI 264 tristate "Reset driver controlled via ARM SCMI interface" 265 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 266 default ARM_SCMI_PROTOCOL 267 help 268 This driver provides support for reset signal/domains that are 269 controlled by firmware that implements the SCMI interface. 270 271 This driver uses SCMI Message Protocol to interact with the 272 firmware controlling all the reset signals. 273 274config RESET_SIMPLE 275 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 276 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 277 depends on HAS_IOMEM 278 help 279 This enables a simple reset controller driver for reset lines that 280 that can be asserted and deasserted by toggling bits in a contiguous, 281 exclusive register space. 282 283 Currently this driver supports: 284 - Altera SoCFPGAs 285 - ASPEED BMC SoCs 286 - Bitmain BM1880 SoC 287 - Realtek SoCs 288 - RCC reset controller in STM32 MCUs 289 - Allwinner SoCs 290 - SiFive FU740 SoCs 291 - Sophgo SoCs 292 293config RESET_SOCFPGA 294 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 295 default ARM && ARCH_INTEL_SOCFPGA 296 select RESET_SIMPLE 297 help 298 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 299 driver gets initialized early during platform init calls. 300 301config RESET_SPACEMIT 302 tristate "SpacemiT reset driver" 303 depends on ARCH_SPACEMIT || COMPILE_TEST 304 select AUXILIARY_BUS 305 default ARCH_SPACEMIT 306 help 307 This enables the reset controller driver for SpacemiT SoCs, 308 including the K1. 309 310config RESET_SUNPLUS 311 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 312 default ARCH_SUNPLUS 313 help 314 This enables the reset driver support for Sunplus SoCs. 315 The reset lines that can be asserted and deasserted by toggling bits 316 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 317 which means each register holds 16 reset lines. 318 319config RESET_SUNXI 320 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 321 default ARCH_SUNXI 322 select RESET_SIMPLE 323 help 324 This enables the reset driver for Allwinner SoCs. 325 326config RESET_TH1520 327 tristate "T-HEAD TH1520 reset controller" 328 depends on ARCH_THEAD || COMPILE_TEST 329 select REGMAP_MMIO 330 help 331 This driver provides support for the T-HEAD TH1520 SoC reset controller, 332 which manages hardware reset lines for SoC components such as the GPU. 333 Enable this option if you need to control hardware resets on TH1520-based 334 systems. 335 336config RESET_TI_SCI 337 tristate "TI System Control Interface (TI-SCI) reset driver" 338 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 339 help 340 This enables the reset driver support over TI System Control Interface 341 available on some new TI's SoCs. If you wish to use reset resources 342 managed by the TI System Controller, say Y here. Otherwise, say N. 343 344config RESET_TI_SYSCON 345 tristate "TI SYSCON Reset Driver" 346 depends on HAS_IOMEM 347 select MFD_SYSCON 348 help 349 This enables the reset driver support for TI devices with 350 memory-mapped reset registers as part of a syscon device node. If 351 you wish to use the reset framework for such memory-mapped devices, 352 say Y here. Otherwise, say N. 353 354config RESET_TI_TPS380X 355 tristate "TI TPS380x Reset Driver" 356 select GPIOLIB 357 help 358 This enables the reset driver support for TI TPS380x devices. If 359 you wish to use the reset framework for such devices, say Y here. 360 Otherwise, say N. 361 362config RESET_TN48M_CPLD 363 tristate "Delta Networks TN48M switch CPLD reset controller" 364 depends on MFD_TN48M_CPLD || COMPILE_TEST 365 default MFD_TN48M_CPLD 366 help 367 This enables the reset controller driver for the Delta TN48M CPLD. 368 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 369 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 370 Microchip PD69200 PoE PSE controller. 371 372 This driver can also be built as a module. If so, the module will be 373 called reset-tn48m. 374 375config RESET_UNIPHIER 376 tristate "Reset controller driver for UniPhier SoCs" 377 depends on ARCH_UNIPHIER || COMPILE_TEST 378 depends on OF && MFD_SYSCON 379 default ARCH_UNIPHIER 380 help 381 Support for reset controllers on UniPhier SoCs. 382 Say Y if you want to control reset signals provided by System Control 383 block, Media I/O block, Peripheral Block. 384 385config RESET_UNIPHIER_GLUE 386 tristate "Reset driver in glue layer for UniPhier SoCs" 387 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 388 default ARCH_UNIPHIER 389 select RESET_SIMPLE 390 help 391 Support for peripheral core reset included in its own glue layer 392 on UniPhier SoCs. Say Y if you want to control reset signals 393 provided by the glue layer. 394 395config RESET_ZYNQ 396 bool "ZYNQ Reset Driver" if COMPILE_TEST 397 default ARCH_ZYNQ 398 help 399 This enables the reset controller driver for Xilinx Zynq SoCs. 400 401config RESET_ZYNQMP 402 bool "ZYNQMP Reset Driver" if COMPILE_TEST 403 default ARCH_ZYNQMP 404 help 405 This enables the reset controller driver for Xilinx ZynqMP SoCs. 406 407source "drivers/reset/amlogic/Kconfig" 408source "drivers/reset/starfive/Kconfig" 409source "drivers/reset/sti/Kconfig" 410source "drivers/reset/hisilicon/Kconfig" 411source "drivers/reset/tegra/Kconfig" 412 413endif 414