1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ASPEED 26 tristate "ASPEED Reset Driver" 27 depends on ARCH_ASPEED || COMPILE_TEST 28 select AUXILIARY_BUS 29 help 30 This enables the reset controller driver for AST2700. 31 32config RESET_ATH79 33 bool "AR71xx Reset Driver" if COMPILE_TEST 34 default ATH79 35 help 36 This enables the ATH79 reset controller driver that supports the 37 AR71xx SoC reset controller. 38 39config RESET_AXS10X 40 bool "AXS10x Reset Driver" if COMPILE_TEST 41 default ARC_PLAT_AXS10X 42 help 43 This enables the reset controller driver for AXS10x. 44 45config RESET_BCM6345 46 bool "BCM6345 Reset Controller" 47 depends on BMIPS_GENERIC || COMPILE_TEST 48 default BMIPS_GENERIC 49 help 50 This enables the reset controller driver for BCM6345 SoCs. 51 52config RESET_BERLIN 53 tristate "Berlin Reset Driver" 54 depends on ARCH_BERLIN || COMPILE_TEST 55 default m if ARCH_BERLIN 56 help 57 This enables the reset controller driver for Marvell Berlin SoCs. 58 59config RESET_BRCMSTB 60 tristate "Broadcom STB reset controller" 61 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 62 default ARCH_BRCMSTB || ARCH_BCM2835 63 help 64 This enables the reset controller driver for Broadcom STB SoCs using 65 a SUN_TOP_CTRL_SW_INIT style controller. 66 67config RESET_BRCMSTB_RESCAL 68 tristate "Broadcom STB RESCAL reset controller" 69 depends on HAS_IOMEM 70 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 71 default ARCH_BRCMSTB || ARCH_BCM2835 72 help 73 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 74 BCM7216 or the BCM2712. 75 76config RESET_EIC7700 77 bool "Reset controller driver for ESWIN SoCs" 78 depends on ARCH_ESWIN || COMPILE_TEST 79 default ARCH_ESWIN 80 help 81 This enables the reset controller driver for ESWIN SoCs. This driver is 82 specific to ESWIN SoCs and should only be enabled if using such hardware. 83 The driver supports eic7700 series chips and provides functionality for 84 asserting and deasserting resets on the chip. 85 86config RESET_EIC7700_HSP 87 tristate "EIC7700 HSP Reset controller" 88 depends on ARCH_ESWIN || COMPILE_TEST 89 select AUXILIARY_BUS 90 help 91 This enables the HSP reset controller driver for ESWIN SoCs. This 92 driver is specific to ESWIN SoCs and should only be enabled if using 93 such hardware. 94 The driver supports EIC7700 series chips and provides functionality 95 for asserting and deasserting resets on the chip. 96 97config RESET_EYEQ 98 bool "Mobileye EyeQ reset controller" 99 depends on EYEQ || COMPILE_TEST 100 select AUXILIARY_BUS 101 default EYEQ 102 help 103 This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L 104 and EyeQ6H SoCs. 105 106 It has one or more domains, with a varying number of resets in each. 107 Registers are located in a shared register region called OLB. EyeQ6H 108 has multiple reset instances. 109 110config RESET_GPIO 111 tristate "GPIO reset controller" 112 depends on GPIOLIB 113 select AUXILIARY_BUS 114 help 115 This enables a generic reset controller for resets attached via 116 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 117 property. 118 119 If compiled as module, it will be called reset-gpio. 120 121config RESET_HSDK 122 bool "Synopsys HSDK Reset Driver" 123 depends on HAS_IOMEM 124 depends on ARC_SOC_HSDK || COMPILE_TEST 125 help 126 This enables the reset controller driver for HSDK board. 127 128config RESET_IMX_SCU 129 tristate "i.MX8Q Reset Driver" 130 depends on IMX_SCU && HAVE_ARM_SMCCC 131 depends on (ARM64 && ARCH_MXC) || COMPILE_TEST 132 help 133 This enables the reset controller driver for i.MX8QM/i.MX8QXP 134 135config RESET_IMX7 136 tristate "i.MX7/8 Reset Driver" 137 depends on HAS_IOMEM 138 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 139 default y if SOC_IMX7D 140 select MFD_SYSCON 141 help 142 This enables the reset controller driver for i.MX7 SoCs. 143 144config RESET_IMX8MP_AUDIOMIX 145 tristate "i.MX8MP AudioMix Reset Driver" 146 depends on ARCH_MXC || COMPILE_TEST 147 select AUXILIARY_BUS 148 default CLK_IMX8MP 149 help 150 This enables the reset controller driver for i.MX8MP AudioMix 151 152config RESET_INTEL_GW 153 bool "Intel Reset Controller Driver" 154 depends on X86 || COMPILE_TEST 155 depends on OF && HAS_IOMEM 156 select REGMAP_MMIO 157 help 158 This enables the reset controller driver for Intel Gateway SoCs. 159 Say Y to control the reset signals provided by reset controller. 160 Otherwise, say N. 161 162config RESET_K210 163 bool "Reset controller driver for Canaan Kendryte K210 SoC" 164 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 165 select MFD_SYSCON 166 default SOC_CANAAN_K210 167 help 168 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 169 Say Y if you want to control reset signals provided by this 170 controller. 171 172config RESET_K230 173 tristate "Reset controller driver for Canaan Kendryte K230 SoC" 174 depends on ARCH_CANAAN || COMPILE_TEST 175 default ARCH_CANAAN 176 help 177 Support for the Canaan Kendryte K230 RISC-V SoC reset controller. 178 Say Y if you want to control reset signals provided by this 179 controller. 180 181config RESET_LANTIQ 182 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 183 default SOC_TYPE_XWAY 184 help 185 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 186 187config RESET_LPC18XX 188 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 189 default ARCH_LPC18XX 190 help 191 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 192 193config RESET_MCHP_SPARX5 194 tristate "Microchip Sparx5 reset driver" 195 depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 196 default y if SPARX5_SWITCH 197 select MFD_SYSCON 198 help 199 This driver supports switch core reset for the Microchip Sparx5 SoC. 200 201config RESET_NPCM 202 bool "NPCM BMC Reset Driver" if COMPILE_TEST 203 default ARCH_NPCM 204 select AUXILIARY_BUS 205 help 206 This enables the reset controller driver for Nuvoton NPCM 207 BMC SoCs. 208 209config RESET_NUVOTON_MA35D1 210 bool "Nuvoton MA35D1 Reset Driver" 211 depends on ARCH_MA35 || COMPILE_TEST 212 default ARCH_MA35 213 help 214 This enables the reset controller driver for Nuvoton MA35D1 SoC. 215 216config RESET_PISTACHIO 217 bool "Pistachio Reset Driver" 218 depends on MIPS || COMPILE_TEST 219 help 220 This enables the reset driver for ImgTec Pistachio SoCs. 221 222config RESET_POLARFIRE_SOC 223 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 224 depends on MCHP_CLK_MPFS 225 depends on MFD_SYSCON 226 select AUXILIARY_BUS 227 default MCHP_CLK_MPFS 228 help 229 This driver supports peripheral reset for the Microchip PolarFire SoC 230 231config RESET_QCOM_AOSS 232 tristate "Qcom AOSS Reset Driver" 233 depends on ARCH_QCOM || COMPILE_TEST 234 help 235 This enables the AOSS (always on subsystem) reset driver 236 for Qualcomm SDM845 SoCs. Say Y if you want to control 237 reset signals provided by AOSS for Modem, Venus, ADSP, 238 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 239 240config RESET_QCOM_PDC 241 tristate "Qualcomm PDC Reset Driver" 242 depends on ARCH_QCOM || COMPILE_TEST 243 help 244 This enables the PDC (Power Domain Controller) reset driver 245 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 246 to control reset signals provided by PDC for Modem, Compute, 247 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 248 249config RESET_RASPBERRYPI 250 tristate "Raspberry Pi 4 Firmware Reset Driver" 251 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 252 default USB_XHCI_PCI 253 help 254 Raspberry Pi 4's co-processor controls some of the board's HW 255 initialization process, but it's up to Linux to trigger it when 256 relevant. This driver provides a reset controller capable of 257 interfacing with RPi4's co-processor and model these firmware 258 initialization routines as reset lines. 259 260config RESET_RZG2L_USBPHY_CTRL 261 tristate "Renesas RZ/G2L USBPHY control driver" 262 depends on ARCH_RZG2L || COMPILE_TEST 263 select MFD_SYSCON 264 help 265 Support for USBPHY Control found on RZ/G2L family. It mainly 266 controls reset and power down of the USB/PHY. 267 268config RESET_RZV2H_USB2PHY 269 tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" 270 depends on ARCH_RENESAS || COMPILE_TEST 271 select AUXILIARY_BUS 272 select REGMAP_MMIO 273 help 274 Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC 275 (and similar SoCs). 276 277config RESET_SCMI 278 tristate "Reset driver controlled via ARM SCMI interface" 279 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 280 default ARM_SCMI_PROTOCOL 281 help 282 This driver provides support for reset signal/domains that are 283 controlled by firmware that implements the SCMI interface. 284 285 This driver uses SCMI Message Protocol to interact with the 286 firmware controlling all the reset signals. 287 288config RESET_SIMPLE 289 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 290 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 291 depends on HAS_IOMEM 292 help 293 This enables a simple reset controller driver for reset lines that 294 that can be asserted and deasserted by toggling bits in a contiguous, 295 exclusive register space. 296 297 Currently this driver supports: 298 - Altera SoCFPGAs 299 - ASPEED BMC SoCs 300 - Bitmain BM1880 SoC 301 - Realtek SoCs 302 - RCC reset controller in STM32 MCUs 303 - Allwinner SoCs 304 - SiFive FU740 SoCs 305 - Sophgo SoCs 306 307config RESET_SKY1 308 bool "Cix Sky1 reset controller" 309 depends on ARCH_CIX || COMPILE_TEST 310 select REGMAP_MMIO 311 help 312 This enables the reset controller for Cix Sky1. 313 314config RESET_SKY1_AUDSS 315 tristate "Cix Sky1 Audio Subsystem reset controller" 316 depends on ARCH_CIX || COMPILE_TEST 317 select AUXILIARY_BUS 318 default CLK_SKY1_AUDSS 319 help 320 Support for block-level software reset lines in the Cix Sky1 321 Audio Subsystem (AUDSS) Clock and Reset Unit. Sixteen reset 322 outputs for audio peripherals are controlled through the CRU 323 register map. The driver binds as an auxiliary device from 324 the AUDSS clock driver. Say M or Y here if you want to build 325 this driver. 326 327config RESET_SOCFPGA 328 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 329 default ARM && ARCH_INTEL_SOCFPGA 330 select RESET_SIMPLE 331 help 332 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 333 driver gets initialized early during platform init calls. 334 335config RESET_SUNPLUS 336 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 337 default ARCH_SUNPLUS 338 help 339 This enables the reset driver support for Sunplus SoCs. 340 The reset lines that can be asserted and deasserted by toggling bits 341 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 342 which means each register holds 16 reset lines. 343 344config RESET_SUNXI 345 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 346 default ARCH_SUNXI 347 select RESET_SIMPLE 348 help 349 This enables the reset driver for Allwinner SoCs. 350 351config RESET_TENSTORRENT_ATLANTIS 352 tristate "Tenstorrent atlantis reset driver" 353 depends on ARCH_TENSTORRENT || COMPILE_TEST 354 select AUXILIARY_BUS 355 default ARCH_TENSTORRENT 356 help 357 This enables the driver for the reset controller 358 present in the Tenstorrent Atlantis SoC. 359 Enable this option to be able to use hardware 360 resets on Atalantis based systems. 361 362config RESET_TH1520 363 tristate "T-HEAD TH1520 reset controller" 364 depends on ARCH_THEAD || COMPILE_TEST 365 select REGMAP_MMIO 366 help 367 This driver provides support for the T-HEAD TH1520 SoC reset controller, 368 which manages hardware reset lines for SoC components such as the GPU. 369 Enable this option if you need to control hardware resets on TH1520-based 370 systems. 371 372config RESET_TI_SCI 373 tristate "TI System Control Interface (TI-SCI) reset driver" 374 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 375 help 376 This enables the reset driver support over TI System Control Interface 377 available on some new TI's SoCs. If you wish to use reset resources 378 managed by the TI System Controller, say Y here. Otherwise, say N. 379 380config RESET_TI_SYSCON 381 tristate "TI SYSCON Reset Driver" 382 depends on HAS_IOMEM 383 select MFD_SYSCON 384 help 385 This enables the reset driver support for TI devices with 386 memory-mapped reset registers as part of a syscon device node. If 387 you wish to use the reset framework for such memory-mapped devices, 388 say Y here. Otherwise, say N. 389 390config RESET_TI_TPS380X 391 tristate "TI TPS380x Reset Driver" 392 select GPIOLIB 393 help 394 This enables the reset driver support for TI TPS380x devices. If 395 you wish to use the reset framework for such devices, say Y here. 396 Otherwise, say N. 397 398config RESET_TN48M_CPLD 399 tristate "Delta Networks TN48M switch CPLD reset controller" 400 depends on MFD_TN48M_CPLD || COMPILE_TEST 401 default MFD_TN48M_CPLD 402 help 403 This enables the reset controller driver for the Delta TN48M CPLD. 404 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 405 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 406 Microchip PD69200 PoE PSE controller. 407 408 This driver can also be built as a module. If so, the module will be 409 called reset-tn48m. 410 411config RESET_UNIPHIER 412 tristate "Reset controller driver for UniPhier SoCs" 413 depends on ARCH_UNIPHIER || COMPILE_TEST 414 depends on OF && MFD_SYSCON 415 default ARCH_UNIPHIER 416 help 417 Support for reset controllers on UniPhier SoCs. 418 Say Y if you want to control reset signals provided by System Control 419 block, Media I/O block, Peripheral Block. 420 421config RESET_UNIPHIER_GLUE 422 tristate "Reset driver in glue layer for UniPhier SoCs" 423 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 424 default ARCH_UNIPHIER 425 select RESET_SIMPLE 426 help 427 Support for peripheral core reset included in its own glue layer 428 on UniPhier SoCs. Say Y if you want to control reset signals 429 provided by the glue layer. 430 431config RESET_ZYNQ 432 bool "ZYNQ Reset Driver" if COMPILE_TEST 433 default ARCH_ZYNQ 434 help 435 This enables the reset controller driver for Xilinx Zynq SoCs. 436 437config RESET_ZYNQMP 438 bool "ZYNQMP Reset Driver" if COMPILE_TEST 439 default ARCH_ZYNQMP 440 help 441 This enables the reset controller driver for Xilinx ZynqMP SoCs. 442 443source "drivers/reset/amlogic/Kconfig" 444source "drivers/reset/hisilicon/Kconfig" 445source "drivers/reset/spacemit/Kconfig" 446source "drivers/reset/starfive/Kconfig" 447source "drivers/reset/sti/Kconfig" 448source "drivers/reset/tegra/Kconfig" 449 450endif 451