1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BCM6345 39 bool "BCM6345 Reset Controller" 40 depends on BMIPS_GENERIC || COMPILE_TEST 41 default BMIPS_GENERIC 42 help 43 This enables the reset controller driver for BCM6345 SoCs. 44 45config RESET_BERLIN 46 tristate "Berlin Reset Driver" 47 depends on ARCH_BERLIN || COMPILE_TEST 48 default m if ARCH_BERLIN 49 help 50 This enables the reset controller driver for Marvell Berlin SoCs. 51 52config RESET_BRCMSTB 53 tristate "Broadcom STB reset controller" 54 depends on ARCH_BRCMSTB || COMPILE_TEST 55 default ARCH_BRCMSTB 56 help 57 This enables the reset controller driver for Broadcom STB SoCs using 58 a SUN_TOP_CTRL_SW_INIT style controller. 59 60config RESET_BRCMSTB_RESCAL 61 tristate "Broadcom STB RESCAL reset controller" 62 depends on HAS_IOMEM 63 depends on ARCH_BRCMSTB || COMPILE_TEST 64 default ARCH_BRCMSTB 65 help 66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 67 BCM7216. 68 69config RESET_GPIO 70 tristate "GPIO reset controller" 71 depends on GPIOLIB 72 help 73 This enables a generic reset controller for resets attached via 74 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 75 property. 76 77 If compiled as module, it will be called reset-gpio. 78 79config RESET_HSDK 80 bool "Synopsys HSDK Reset Driver" 81 depends on HAS_IOMEM 82 depends on ARC_SOC_HSDK || COMPILE_TEST 83 help 84 This enables the reset controller driver for HSDK board. 85 86config RESET_IMX7 87 tristate "i.MX7/8 Reset Driver" 88 depends on HAS_IOMEM 89 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 90 default y if SOC_IMX7D 91 select MFD_SYSCON 92 help 93 This enables the reset controller driver for i.MX7 SoCs. 94 95config RESET_INTEL_GW 96 bool "Intel Reset Controller Driver" 97 depends on X86 || COMPILE_TEST 98 depends on OF && HAS_IOMEM 99 select REGMAP_MMIO 100 help 101 This enables the reset controller driver for Intel Gateway SoCs. 102 Say Y to control the reset signals provided by reset controller. 103 Otherwise, say N. 104 105config RESET_K210 106 bool "Reset controller driver for Canaan Kendryte K210 SoC" 107 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 108 select MFD_SYSCON 109 default SOC_CANAAN_K210 110 help 111 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 112 Say Y if you want to control reset signals provided by this 113 controller. 114 115config RESET_LANTIQ 116 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 117 default SOC_TYPE_XWAY 118 help 119 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 120 121config RESET_LPC18XX 122 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 123 default ARCH_LPC18XX 124 help 125 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 126 127config RESET_MCHP_SPARX5 128 bool "Microchip Sparx5 reset driver" 129 depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST 130 default y if SPARX5_SWITCH 131 select MFD_SYSCON 132 help 133 This driver supports switch core reset for the Microchip Sparx5 SoC. 134 135config RESET_MESON 136 tristate "Meson Reset Driver" 137 depends on ARCH_MESON || COMPILE_TEST 138 default ARCH_MESON 139 help 140 This enables the reset driver for Amlogic Meson SoCs. 141 142config RESET_MESON_AUDIO_ARB 143 tristate "Meson Audio Memory Arbiter Reset Driver" 144 depends on ARCH_MESON || COMPILE_TEST 145 help 146 This enables the reset driver for Audio Memory Arbiter of 147 Amlogic's A113 based SoCs 148 149config RESET_NPCM 150 bool "NPCM BMC Reset Driver" if COMPILE_TEST 151 default ARCH_NPCM 152 help 153 This enables the reset controller driver for Nuvoton NPCM 154 BMC SoCs. 155 156config RESET_NUVOTON_MA35D1 157 bool "Nuvoton MA35D1 Reset Driver" 158 depends on ARCH_MA35 || COMPILE_TEST 159 default ARCH_MA35 160 help 161 This enables the reset controller driver for Nuvoton MA35D1 SoC. 162 163config RESET_PISTACHIO 164 bool "Pistachio Reset Driver" 165 depends on MIPS || COMPILE_TEST 166 help 167 This enables the reset driver for ImgTec Pistachio SoCs. 168 169config RESET_POLARFIRE_SOC 170 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 171 depends on MCHP_CLK_MPFS 172 select AUXILIARY_BUS 173 default MCHP_CLK_MPFS 174 help 175 This driver supports peripheral reset for the Microchip PolarFire SoC 176 177config RESET_QCOM_AOSS 178 tristate "Qcom AOSS Reset Driver" 179 depends on ARCH_QCOM || COMPILE_TEST 180 help 181 This enables the AOSS (always on subsystem) reset driver 182 for Qualcomm SDM845 SoCs. Say Y if you want to control 183 reset signals provided by AOSS for Modem, Venus, ADSP, 184 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 185 186config RESET_QCOM_PDC 187 tristate "Qualcomm PDC Reset Driver" 188 depends on ARCH_QCOM || COMPILE_TEST 189 help 190 This enables the PDC (Power Domain Controller) reset driver 191 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 192 to control reset signals provided by PDC for Modem, Compute, 193 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 194 195config RESET_RASPBERRYPI 196 tristate "Raspberry Pi 4 Firmware Reset Driver" 197 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 198 default USB_XHCI_PCI 199 help 200 Raspberry Pi 4's co-processor controls some of the board's HW 201 initialization process, but it's up to Linux to trigger it when 202 relevant. This driver provides a reset controller capable of 203 interfacing with RPi4's co-processor and model these firmware 204 initialization routines as reset lines. 205 206config RESET_RZG2L_USBPHY_CTRL 207 tristate "Renesas RZ/G2L USBPHY control driver" 208 depends on ARCH_RZG2L || COMPILE_TEST 209 help 210 Support for USBPHY Control found on RZ/G2L family. It mainly 211 controls reset and power down of the USB/PHY. 212 213config RESET_SCMI 214 tristate "Reset driver controlled via ARM SCMI interface" 215 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 216 default ARM_SCMI_PROTOCOL 217 help 218 This driver provides support for reset signal/domains that are 219 controlled by firmware that implements the SCMI interface. 220 221 This driver uses SCMI Message Protocol to interact with the 222 firmware controlling all the reset signals. 223 224config RESET_SIMPLE 225 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 226 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 227 depends on HAS_IOMEM 228 help 229 This enables a simple reset controller driver for reset lines that 230 that can be asserted and deasserted by toggling bits in a contiguous, 231 exclusive register space. 232 233 Currently this driver supports: 234 - Altera SoCFPGAs 235 - ASPEED BMC SoCs 236 - Bitmain BM1880 SoC 237 - Realtek SoCs 238 - RCC reset controller in STM32 MCUs 239 - Allwinner SoCs 240 - SiFive FU740 SoCs 241 - Sophgo SoCs 242 243config RESET_SOCFPGA 244 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 245 default ARM && ARCH_INTEL_SOCFPGA 246 select RESET_SIMPLE 247 help 248 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 249 driver gets initialized early during platform init calls. 250 251config RESET_SUNPLUS 252 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 253 default ARCH_SUNPLUS 254 help 255 This enables the reset driver support for Sunplus SoCs. 256 The reset lines that can be asserted and deasserted by toggling bits 257 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 258 which means each register holds 16 reset lines. 259 260config RESET_SUNXI 261 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 262 default ARCH_SUNXI 263 select RESET_SIMPLE 264 help 265 This enables the reset driver for Allwinner SoCs. 266 267config RESET_TI_SCI 268 tristate "TI System Control Interface (TI-SCI) reset driver" 269 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 270 help 271 This enables the reset driver support over TI System Control Interface 272 available on some new TI's SoCs. If you wish to use reset resources 273 managed by the TI System Controller, say Y here. Otherwise, say N. 274 275config RESET_TI_SYSCON 276 tristate "TI SYSCON Reset Driver" 277 depends on HAS_IOMEM 278 select MFD_SYSCON 279 help 280 This enables the reset driver support for TI devices with 281 memory-mapped reset registers as part of a syscon device node. If 282 you wish to use the reset framework for such memory-mapped devices, 283 say Y here. Otherwise, say N. 284 285config RESET_TI_TPS380X 286 tristate "TI TPS380x Reset Driver" 287 select GPIOLIB 288 help 289 This enables the reset driver support for TI TPS380x devices. If 290 you wish to use the reset framework for such devices, say Y here. 291 Otherwise, say N. 292 293config RESET_TN48M_CPLD 294 tristate "Delta Networks TN48M switch CPLD reset controller" 295 depends on MFD_TN48M_CPLD || COMPILE_TEST 296 default MFD_TN48M_CPLD 297 help 298 This enables the reset controller driver for the Delta TN48M CPLD. 299 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 300 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 301 Microchip PD69200 PoE PSE controller. 302 303 This driver can also be built as a module. If so, the module will be 304 called reset-tn48m. 305 306config RESET_UNIPHIER 307 tristate "Reset controller driver for UniPhier SoCs" 308 depends on ARCH_UNIPHIER || COMPILE_TEST 309 depends on OF && MFD_SYSCON 310 default ARCH_UNIPHIER 311 help 312 Support for reset controllers on UniPhier SoCs. 313 Say Y if you want to control reset signals provided by System Control 314 block, Media I/O block, Peripheral Block. 315 316config RESET_UNIPHIER_GLUE 317 tristate "Reset driver in glue layer for UniPhier SoCs" 318 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 319 default ARCH_UNIPHIER 320 select RESET_SIMPLE 321 help 322 Support for peripheral core reset included in its own glue layer 323 on UniPhier SoCs. Say Y if you want to control reset signals 324 provided by the glue layer. 325 326config RESET_ZYNQ 327 bool "ZYNQ Reset Driver" if COMPILE_TEST 328 default ARCH_ZYNQ 329 help 330 This enables the reset controller driver for Xilinx Zynq SoCs. 331 332source "drivers/reset/starfive/Kconfig" 333source "drivers/reset/sti/Kconfig" 334source "drivers/reset/hisilicon/Kconfig" 335source "drivers/reset/tegra/Kconfig" 336 337endif 338