1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BCM6345 39 bool "BCM6345 Reset Controller" 40 depends on BMIPS_GENERIC || COMPILE_TEST 41 default BMIPS_GENERIC 42 help 43 This enables the reset controller driver for BCM6345 SoCs. 44 45config RESET_BERLIN 46 tristate "Berlin Reset Driver" 47 depends on ARCH_BERLIN || COMPILE_TEST 48 default m if ARCH_BERLIN 49 help 50 This enables the reset controller driver for Marvell Berlin SoCs. 51 52config RESET_BRCMSTB 53 tristate "Broadcom STB reset controller" 54 depends on ARCH_BRCMSTB || COMPILE_TEST 55 default ARCH_BRCMSTB 56 help 57 This enables the reset controller driver for Broadcom STB SoCs using 58 a SUN_TOP_CTRL_SW_INIT style controller. 59 60config RESET_BRCMSTB_RESCAL 61 tristate "Broadcom STB RESCAL reset controller" 62 depends on HAS_IOMEM 63 depends on ARCH_BRCMSTB || COMPILE_TEST 64 default ARCH_BRCMSTB 65 help 66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 67 BCM7216. 68 69config RESET_GPIO 70 tristate "GPIO reset controller" 71 help 72 This enables a generic reset controller for resets attached via 73 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 74 property. 75 76 If compiled as module, it will be called reset-gpio. 77 78config RESET_HSDK 79 bool "Synopsys HSDK Reset Driver" 80 depends on HAS_IOMEM 81 depends on ARC_SOC_HSDK || COMPILE_TEST 82 help 83 This enables the reset controller driver for HSDK board. 84 85config RESET_IMX7 86 tristate "i.MX7/8 Reset Driver" 87 depends on HAS_IOMEM 88 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 89 default y if SOC_IMX7D 90 select MFD_SYSCON 91 help 92 This enables the reset controller driver for i.MX7 SoCs. 93 94config RESET_IMX8MP_AUDIOMIX 95 tristate "i.MX8MP AudioMix Reset Driver" 96 depends on ARCH_MXC || COMPILE_TEST 97 select AUXILIARY_BUS 98 default CLK_IMX8MP 99 help 100 This enables the reset controller driver for i.MX8MP AudioMix 101 102config RESET_INTEL_GW 103 bool "Intel Reset Controller Driver" 104 depends on X86 || COMPILE_TEST 105 depends on OF && HAS_IOMEM 106 select REGMAP_MMIO 107 help 108 This enables the reset controller driver for Intel Gateway SoCs. 109 Say Y to control the reset signals provided by reset controller. 110 Otherwise, say N. 111 112config RESET_K210 113 bool "Reset controller driver for Canaan Kendryte K210 SoC" 114 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 115 select MFD_SYSCON 116 default SOC_CANAAN_K210 117 help 118 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 119 Say Y if you want to control reset signals provided by this 120 controller. 121 122config RESET_LANTIQ 123 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 124 default SOC_TYPE_XWAY 125 help 126 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 127 128config RESET_LPC18XX 129 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 130 default ARCH_LPC18XX 131 help 132 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 133 134config RESET_MCHP_SPARX5 135 bool "Microchip Sparx5 reset driver" 136 depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST 137 default y if SPARX5_SWITCH 138 select MFD_SYSCON 139 help 140 This driver supports switch core reset for the Microchip Sparx5 SoC. 141 142config RESET_MESON 143 tristate "Meson Reset Driver" 144 depends on ARCH_MESON || COMPILE_TEST 145 default ARCH_MESON 146 help 147 This enables the reset driver for Amlogic Meson SoCs. 148 149config RESET_MESON_AUDIO_ARB 150 tristate "Meson Audio Memory Arbiter Reset Driver" 151 depends on ARCH_MESON || COMPILE_TEST 152 help 153 This enables the reset driver for Audio Memory Arbiter of 154 Amlogic's A113 based SoCs 155 156config RESET_NPCM 157 bool "NPCM BMC Reset Driver" if COMPILE_TEST 158 default ARCH_NPCM 159 help 160 This enables the reset controller driver for Nuvoton NPCM 161 BMC SoCs. 162 163config RESET_NUVOTON_MA35D1 164 bool "Nuvoton MA35D1 Reset Driver" 165 depends on ARCH_MA35 || COMPILE_TEST 166 default ARCH_MA35 167 help 168 This enables the reset controller driver for Nuvoton MA35D1 SoC. 169 170config RESET_PISTACHIO 171 bool "Pistachio Reset Driver" 172 depends on MIPS || COMPILE_TEST 173 help 174 This enables the reset driver for ImgTec Pistachio SoCs. 175 176config RESET_POLARFIRE_SOC 177 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 178 depends on MCHP_CLK_MPFS 179 select AUXILIARY_BUS 180 default MCHP_CLK_MPFS 181 help 182 This driver supports peripheral reset for the Microchip PolarFire SoC 183 184config RESET_QCOM_AOSS 185 tristate "Qcom AOSS Reset Driver" 186 depends on ARCH_QCOM || COMPILE_TEST 187 help 188 This enables the AOSS (always on subsystem) reset driver 189 for Qualcomm SDM845 SoCs. Say Y if you want to control 190 reset signals provided by AOSS for Modem, Venus, ADSP, 191 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 192 193config RESET_QCOM_PDC 194 tristate "Qualcomm PDC Reset Driver" 195 depends on ARCH_QCOM || COMPILE_TEST 196 help 197 This enables the PDC (Power Domain Controller) reset driver 198 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 199 to control reset signals provided by PDC for Modem, Compute, 200 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 201 202config RESET_RASPBERRYPI 203 tristate "Raspberry Pi 4 Firmware Reset Driver" 204 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 205 default USB_XHCI_PCI 206 help 207 Raspberry Pi 4's co-processor controls some of the board's HW 208 initialization process, but it's up to Linux to trigger it when 209 relevant. This driver provides a reset controller capable of 210 interfacing with RPi4's co-processor and model these firmware 211 initialization routines as reset lines. 212 213config RESET_RZG2L_USBPHY_CTRL 214 tristate "Renesas RZ/G2L USBPHY control driver" 215 depends on ARCH_RZG2L || COMPILE_TEST 216 help 217 Support for USBPHY Control found on RZ/G2L family. It mainly 218 controls reset and power down of the USB/PHY. 219 220config RESET_SCMI 221 tristate "Reset driver controlled via ARM SCMI interface" 222 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 223 default ARM_SCMI_PROTOCOL 224 help 225 This driver provides support for reset signal/domains that are 226 controlled by firmware that implements the SCMI interface. 227 228 This driver uses SCMI Message Protocol to interact with the 229 firmware controlling all the reset signals. 230 231config RESET_SIMPLE 232 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 233 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 234 depends on HAS_IOMEM 235 help 236 This enables a simple reset controller driver for reset lines that 237 that can be asserted and deasserted by toggling bits in a contiguous, 238 exclusive register space. 239 240 Currently this driver supports: 241 - Altera SoCFPGAs 242 - ASPEED BMC SoCs 243 - Bitmain BM1880 SoC 244 - Realtek SoCs 245 - RCC reset controller in STM32 MCUs 246 - Allwinner SoCs 247 - SiFive FU740 SoCs 248 - Sophgo SoCs 249 250config RESET_SOCFPGA 251 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 252 default ARM && ARCH_INTEL_SOCFPGA 253 select RESET_SIMPLE 254 help 255 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 256 driver gets initialized early during platform init calls. 257 258config RESET_SUNPLUS 259 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 260 default ARCH_SUNPLUS 261 help 262 This enables the reset driver support for Sunplus SoCs. 263 The reset lines that can be asserted and deasserted by toggling bits 264 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 265 which means each register holds 16 reset lines. 266 267config RESET_SUNXI 268 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 269 default ARCH_SUNXI 270 select RESET_SIMPLE 271 help 272 This enables the reset driver for Allwinner SoCs. 273 274config RESET_TI_SCI 275 tristate "TI System Control Interface (TI-SCI) reset driver" 276 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 277 help 278 This enables the reset driver support over TI System Control Interface 279 available on some new TI's SoCs. If you wish to use reset resources 280 managed by the TI System Controller, say Y here. Otherwise, say N. 281 282config RESET_TI_SYSCON 283 tristate "TI SYSCON Reset Driver" 284 depends on HAS_IOMEM 285 select MFD_SYSCON 286 help 287 This enables the reset driver support for TI devices with 288 memory-mapped reset registers as part of a syscon device node. If 289 you wish to use the reset framework for such memory-mapped devices, 290 say Y here. Otherwise, say N. 291 292config RESET_TI_TPS380X 293 tristate "TI TPS380x Reset Driver" 294 select GPIOLIB 295 help 296 This enables the reset driver support for TI TPS380x devices. If 297 you wish to use the reset framework for such devices, say Y here. 298 Otherwise, say N. 299 300config RESET_TN48M_CPLD 301 tristate "Delta Networks TN48M switch CPLD reset controller" 302 depends on MFD_TN48M_CPLD || COMPILE_TEST 303 default MFD_TN48M_CPLD 304 help 305 This enables the reset controller driver for the Delta TN48M CPLD. 306 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 307 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 308 Microchip PD69200 PoE PSE controller. 309 310 This driver can also be built as a module. If so, the module will be 311 called reset-tn48m. 312 313config RESET_UNIPHIER 314 tristate "Reset controller driver for UniPhier SoCs" 315 depends on ARCH_UNIPHIER || COMPILE_TEST 316 depends on OF && MFD_SYSCON 317 default ARCH_UNIPHIER 318 help 319 Support for reset controllers on UniPhier SoCs. 320 Say Y if you want to control reset signals provided by System Control 321 block, Media I/O block, Peripheral Block. 322 323config RESET_UNIPHIER_GLUE 324 tristate "Reset driver in glue layer for UniPhier SoCs" 325 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 326 default ARCH_UNIPHIER 327 select RESET_SIMPLE 328 help 329 Support for peripheral core reset included in its own glue layer 330 on UniPhier SoCs. Say Y if you want to control reset signals 331 provided by the glue layer. 332 333config RESET_ZYNQ 334 bool "ZYNQ Reset Driver" if COMPILE_TEST 335 default ARCH_ZYNQ 336 help 337 This enables the reset controller driver for Xilinx Zynq SoCs. 338 339config RESET_ZYNQMP 340 bool "ZYNQMP Reset Driver" if COMPILE_TEST 341 default ARCH_ZYNQMP 342 help 343 This enables the reset controller driver for Xilinx ZynqMP SoCs. 344 345source "drivers/reset/starfive/Kconfig" 346source "drivers/reset/sti/Kconfig" 347source "drivers/reset/hisilicon/Kconfig" 348source "drivers/reset/tegra/Kconfig" 349 350endif 351