xref: /linux/drivers/reset/Kconfig (revision 487b1b32e317b85c2948eb4013f3e089a0433d49)
1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only
261fc4131SPhilipp Zabelconfig ARCH_HAS_RESET_CONTROLLER
361fc4131SPhilipp Zabel	bool
461fc4131SPhilipp Zabel
561fc4131SPhilipp Zabelmenuconfig RESET_CONTROLLER
661fc4131SPhilipp Zabel	bool "Reset Controller Support"
761fc4131SPhilipp Zabel	default y if ARCH_HAS_RESET_CONTROLLER
861fc4131SPhilipp Zabel	help
961fc4131SPhilipp Zabel	  Generic Reset Controller support.
1061fc4131SPhilipp Zabel
1161fc4131SPhilipp Zabel	  This framework is designed to abstract reset handling of devices
1261fc4131SPhilipp Zabel	  via GPIOs or SoC-internal reset controller modules.
1361fc4131SPhilipp Zabel
1461fc4131SPhilipp Zabel	  If unsure, say no.
15e5d76075SStephen Gallimore
16998cd463SMasahiro Yamadaif RESET_CONTROLLER
17998cd463SMasahiro Yamada
1862700682SThor Thayerconfig RESET_A10SR
1962700682SThor Thayer	tristate "Altera Arria10 System Resource Reset"
20af19f193SPhilipp Zabel	depends on MFD_ALTERA_A10SR || COMPILE_TEST
2162700682SThor Thayer	help
2262700682SThor Thayer	  This option enables support for the external reset functions for
2362700682SThor Thayer	  peripheral PHYs on the Altera Arria10 System Resource Chip.
2462700682SThor Thayer
25e27b4a6eSPhilipp Zabelconfig RESET_ATH79
26e27b4a6eSPhilipp Zabel	bool "AR71xx Reset Driver" if COMPILE_TEST
27e27b4a6eSPhilipp Zabel	default ATH79
28e27b4a6eSPhilipp Zabel	help
29e27b4a6eSPhilipp Zabel	  This enables the ATH79 reset controller driver that supports the
30e27b4a6eSPhilipp Zabel	  AR71xx SoC reset controller.
31e27b4a6eSPhilipp Zabel
3237634923SEugeniy Paltsevconfig RESET_AXS10X
3337634923SEugeniy Paltsev	bool "AXS10x Reset Driver" if COMPILE_TEST
3437634923SEugeniy Paltsev	default ARC_PLAT_AXS10X
3537634923SEugeniy Paltsev	help
3637634923SEugeniy Paltsev	  This enables the reset controller driver for AXS10x.
3737634923SEugeniy Paltsev
38aac02543SÁlvaro Fernández Rojasconfig RESET_BCM6345
39aac02543SÁlvaro Fernández Rojas	bool "BCM6345 Reset Controller"
40aac02543SÁlvaro Fernández Rojas	depends on BMIPS_GENERIC || COMPILE_TEST
41aac02543SÁlvaro Fernández Rojas	default BMIPS_GENERIC
42aac02543SÁlvaro Fernández Rojas	help
43aac02543SÁlvaro Fernández Rojas	  This enables the reset controller driver for BCM6345 SoCs.
44aac02543SÁlvaro Fernández Rojas
4570d467eaSPhilipp Zabelconfig RESET_BERLIN
465e787cdfSJisheng Zhang	tristate "Berlin Reset Driver"
475e787cdfSJisheng Zhang	depends on ARCH_BERLIN || COMPILE_TEST
485e787cdfSJisheng Zhang	default m if ARCH_BERLIN
4970d467eaSPhilipp Zabel	help
5070d467eaSPhilipp Zabel	  This enables the reset controller driver for Marvell Berlin SoCs.
5170d467eaSPhilipp Zabel
5277750bc0SFlorian Fainelliconfig RESET_BRCMSTB
5377750bc0SFlorian Fainelli	tristate "Broadcom STB reset controller"
5477750bc0SFlorian Fainelli	depends on ARCH_BRCMSTB || COMPILE_TEST
5577750bc0SFlorian Fainelli	default ARCH_BRCMSTB
5677750bc0SFlorian Fainelli	help
5777750bc0SFlorian Fainelli	  This enables the reset controller driver for Broadcom STB SoCs using
5877750bc0SFlorian Fainelli	  a SUN_TOP_CTRL_SW_INIT style controller.
5977750bc0SFlorian Fainelli
604cf176e5SJim Quinlanconfig RESET_BRCMSTB_RESCAL
615694ca29SFlorian Fainelli	tristate "Broadcom STB RESCAL reset controller"
627fbcc535SBrendan Higgins	depends on HAS_IOMEM
6342f6a76fSGeert Uytterhoeven	depends on ARCH_BRCMSTB || COMPILE_TEST
6442f6a76fSGeert Uytterhoeven	default ARCH_BRCMSTB
654cf176e5SJim Quinlan	help
664cf176e5SJim Quinlan	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
674cf176e5SJim Quinlan	  BCM7216.
684cf176e5SJim Quinlan
69*487b1b32SThéo Lebrunconfig RESET_EYEQ
70*487b1b32SThéo Lebrun	bool "Mobileye EyeQ reset controller"
71*487b1b32SThéo Lebrun	depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
72*487b1b32SThéo Lebrun	select AUXILIARY_BUS
73*487b1b32SThéo Lebrun	default MACH_EYEQ5 || MACH_EYEQ6H
74*487b1b32SThéo Lebrun	help
75*487b1b32SThéo Lebrun	  This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
76*487b1b32SThéo Lebrun	  and EyeQ6H SoCs.
77*487b1b32SThéo Lebrun
78*487b1b32SThéo Lebrun	  It has one or more domains, with a varying number of resets in each.
79*487b1b32SThéo Lebrun	  Registers are located in a shared register region called OLB. EyeQ6H
80*487b1b32SThéo Lebrun	  has multiple reset instances.
81*487b1b32SThéo Lebrun
82cee544a4SKrzysztof Kozlowskiconfig RESET_GPIO
83cee544a4SKrzysztof Kozlowski	tristate "GPIO reset controller"
8401f6a84cSMark Brown	depends on GPIOLIB
85cee544a4SKrzysztof Kozlowski	help
86cee544a4SKrzysztof Kozlowski	  This enables a generic reset controller for resets attached via
87cee544a4SKrzysztof Kozlowski	  GPIOs.  Typically for OF platforms this driver expects "reset-gpios"
88cee544a4SKrzysztof Kozlowski	  property.
89cee544a4SKrzysztof Kozlowski
90cee544a4SKrzysztof Kozlowski	  If compiled as module, it will be called reset-gpio.
91cee544a4SKrzysztof Kozlowski
9213541226SVineet Guptaconfig RESET_HSDK
9313541226SVineet Gupta	bool "Synopsys HSDK Reset Driver"
942d48a237SThomas Meyer	depends on HAS_IOMEM
95544e3bf4SGeert Uytterhoeven	depends on ARC_SOC_HSDK || COMPILE_TEST
96e0be864fSEugeniy Paltsev	help
9713541226SVineet Gupta	  This enables the reset controller driver for HSDK board.
98e0be864fSEugeniy Paltsev
99abf97755SAndrey Smirnovconfig RESET_IMX7
100a442abbbSAnson Huang	tristate "i.MX7/8 Reset Driver"
1018fa56620SMasahiro Yamada	depends on HAS_IOMEM
102a442abbbSAnson Huang	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
103a442abbbSAnson Huang	default y if SOC_IMX7D
104abf97755SAndrey Smirnov	select MFD_SYSCON
105abf97755SAndrey Smirnov	help
106abf97755SAndrey Smirnov	  This enables the reset controller driver for i.MX7 SoCs.
107abf97755SAndrey Smirnov
108fe125601SShengjiu Wangconfig RESET_IMX8MP_AUDIOMIX
109fe125601SShengjiu Wang	tristate "i.MX8MP AudioMix Reset Driver"
110eb5d88b1SGeert Uytterhoeven	depends on ARCH_MXC || COMPILE_TEST
111fe125601SShengjiu Wang	select AUXILIARY_BUS
112fe125601SShengjiu Wang	default CLK_IMX8MP
113fe125601SShengjiu Wang	help
114fe125601SShengjiu Wang	  This enables the reset controller driver for i.MX8MP AudioMix
115fe125601SShengjiu Wang
116c9aef213SDilip Kotaconfig RESET_INTEL_GW
117c9aef213SDilip Kota	bool "Intel Reset Controller Driver"
1186ab9d621SGeert Uytterhoeven	depends on X86 || COMPILE_TEST
119b460e0a9SBrendan Higgins	depends on OF && HAS_IOMEM
120c9aef213SDilip Kota	select REGMAP_MMIO
121c9aef213SDilip Kota	help
122c9aef213SDilip Kota	  This enables the reset controller driver for Intel Gateway SoCs.
123c9aef213SDilip Kota	  Say Y to control the reset signals provided by reset controller.
124c9aef213SDilip Kota	  Otherwise, say N.
125c9aef213SDilip Kota
1265a2308daSDamien Le Moalconfig RESET_K210
1275a2308daSDamien Le Moal	bool "Reset controller driver for Canaan Kendryte K210 SoC"
12868f41105SYangyu Chen	depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF
1295a2308daSDamien Le Moal	select MFD_SYSCON
13068f41105SYangyu Chen	default SOC_CANAAN_K210
1315a2308daSDamien Le Moal	help
1325a2308daSDamien Le Moal	  Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
1335a2308daSDamien Le Moal	  Say Y if you want to control reset signals provided by this
1345a2308daSDamien Le Moal	  controller.
1355a2308daSDamien Le Moal
13679797b6fSMartin Blumenstinglconfig RESET_LANTIQ
13779797b6fSMartin Blumenstingl	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
13879797b6fSMartin Blumenstingl	default SOC_TYPE_XWAY
13979797b6fSMartin Blumenstingl	help
14079797b6fSMartin Blumenstingl	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
14179797b6fSMartin Blumenstingl
142cd7f4b81SPhilipp Zabelconfig RESET_LPC18XX
143cd7f4b81SPhilipp Zabel	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
144cd7f4b81SPhilipp Zabel	default ARCH_LPC18XX
145cd7f4b81SPhilipp Zabel	help
146cd7f4b81SPhilipp Zabel	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
147cd7f4b81SPhilipp Zabel
148453ed428SSteen Hegelundconfig RESET_MCHP_SPARX5
149453ed428SSteen Hegelund	bool "Microchip Sparx5 reset driver"
1508c81620aSHoratiu Vultur	depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
151453ed428SSteen Hegelund	default y if SPARX5_SWITCH
152453ed428SSteen Hegelund	select MFD_SYSCON
153453ed428SSteen Hegelund	help
154453ed428SSteen Hegelund	  This driver supports switch core reset for the Microchip Sparx5 SoC.
155453ed428SSteen Hegelund
15644336c24SPhilipp Zabelconfig RESET_MESON
1573bfe8933SNeil Armstrong	tristate "Meson Reset Driver"
1583bfe8933SNeil Armstrong	depends on ARCH_MESON || COMPILE_TEST
15944336c24SPhilipp Zabel	default ARCH_MESON
16044336c24SPhilipp Zabel	help
16144336c24SPhilipp Zabel	  This enables the reset driver for Amlogic Meson SoCs.
16244336c24SPhilipp Zabel
163d903779bSJerome Brunetconfig RESET_MESON_AUDIO_ARB
164d903779bSJerome Brunet	tristate "Meson Audio Memory Arbiter Reset Driver"
165d903779bSJerome Brunet	depends on ARCH_MESON || COMPILE_TEST
166d903779bSJerome Brunet	help
167d903779bSJerome Brunet	  This enables the reset driver for Audio Memory Arbiter of
168d903779bSJerome Brunet	  Amlogic's A113 based SoCs
169d903779bSJerome Brunet
1709c81b2ccSTomer Maimonconfig RESET_NPCM
1719c81b2ccSTomer Maimon	bool "NPCM BMC Reset Driver" if COMPILE_TEST
1729c81b2ccSTomer Maimon	default ARCH_NPCM
1739c81b2ccSTomer Maimon	help
1749c81b2ccSTomer Maimon	  This enables the reset controller driver for Nuvoton NPCM
1759c81b2ccSTomer Maimon	  BMC SoCs.
1769c81b2ccSTomer Maimon
177e4bb55d6SJacky Huangconfig RESET_NUVOTON_MA35D1
178aead1076SGeert Uytterhoeven	bool "Nuvoton MA35D1 Reset Driver"
179aead1076SGeert Uytterhoeven	depends on ARCH_MA35 || COMPILE_TEST
180aead1076SGeert Uytterhoeven	default ARCH_MA35
181e4bb55d6SJacky Huang	help
182e4bb55d6SJacky Huang	  This enables the reset controller driver for Nuvoton MA35D1 SoC.
183e4bb55d6SJacky Huang
184fab3f730SPhilipp Zabelconfig RESET_PISTACHIO
1854af16070SGeert Uytterhoeven	bool "Pistachio Reset Driver"
1864af16070SGeert Uytterhoeven	depends on MIPS || COMPILE_TEST
187fab3f730SPhilipp Zabel	help
188fab3f730SPhilipp Zabel	  This enables the reset driver for ImgTec Pistachio SoCs.
189fab3f730SPhilipp Zabel
19005f9e363SConor Dooleyconfig RESET_POLARFIRE_SOC
19105f9e363SConor Dooley	bool "Microchip PolarFire SoC (MPFS) Reset Driver"
192afb39e2bSPhilipp Zabel	depends on MCHP_CLK_MPFS
193afb39e2bSPhilipp Zabel	select AUXILIARY_BUS
19405f9e363SConor Dooley	default MCHP_CLK_MPFS
19505f9e363SConor Dooley	help
19605f9e363SConor Dooley	  This driver supports peripheral reset for the Microchip PolarFire SoC
19705f9e363SConor Dooley
1985ecb0651SSibi Sankarconfig RESET_QCOM_AOSS
199e2d5e833SJohn Stultz	tristate "Qcom AOSS Reset Driver"
2005ecb0651SSibi Sankar	depends on ARCH_QCOM || COMPILE_TEST
2015ecb0651SSibi Sankar	help
2025ecb0651SSibi Sankar	  This enables the AOSS (always on subsystem) reset driver
2035ecb0651SSibi Sankar	  for Qualcomm SDM845 SoCs. Say Y if you want to control
2045ecb0651SSibi Sankar	  reset signals provided by AOSS for Modem, Venus, ADSP,
2055ecb0651SSibi Sankar	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
2065ecb0651SSibi Sankar
207eea2926bSSibi Sankarconfig RESET_QCOM_PDC
208eea2926bSSibi Sankar	tristate "Qualcomm PDC Reset Driver"
209eea2926bSSibi Sankar	depends on ARCH_QCOM || COMPILE_TEST
210eea2926bSSibi Sankar	help
211eea2926bSSibi Sankar	  This enables the PDC (Power Domain Controller) reset driver
212eea2926bSSibi Sankar	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
213eea2926bSSibi Sankar	  to control reset signals provided by PDC for Modem, Compute,
214eea2926bSSibi Sankar	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
215eea2926bSSibi Sankar
216abffc82aSNicolas Saenz Julienneconfig RESET_RASPBERRYPI
217abffc82aSNicolas Saenz Julienne	tristate "Raspberry Pi 4 Firmware Reset Driver"
218abffc82aSNicolas Saenz Julienne	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
219abffc82aSNicolas Saenz Julienne	default USB_XHCI_PCI
220abffc82aSNicolas Saenz Julienne	help
221abffc82aSNicolas Saenz Julienne	  Raspberry Pi 4's co-processor controls some of the board's HW
222abffc82aSNicolas Saenz Julienne	  initialization process, but it's up to Linux to trigger it when
223abffc82aSNicolas Saenz Julienne	  relevant. This driver provides a reset controller capable of
224abffc82aSNicolas Saenz Julienne	  interfacing with RPi4's co-processor and model these firmware
225abffc82aSNicolas Saenz Julienne	  initialization routines as reset lines.
226abffc82aSNicolas Saenz Julienne
227bee08559SBiju Dasconfig RESET_RZG2L_USBPHY_CTRL
228bee08559SBiju Das	tristate "Renesas RZ/G2L USBPHY control driver"
2299fe7dd4eSLad Prabhakar	depends on ARCH_RZG2L || COMPILE_TEST
230bee08559SBiju Das	help
231bee08559SBiju Das	  Support for USBPHY Control found on RZ/G2L family. It mainly
232bee08559SBiju Das	  controls reset and power down of the USB/PHY.
233bee08559SBiju Das
234c8ae9c2dSSudeep Hollaconfig RESET_SCMI
235c8ae9c2dSSudeep Holla	tristate "Reset driver controlled via ARM SCMI interface"
236c8ae9c2dSSudeep Holla	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
237c8ae9c2dSSudeep Holla	default ARM_SCMI_PROTOCOL
238c8ae9c2dSSudeep Holla	help
239c8ae9c2dSSudeep Holla	  This driver provides support for reset signal/domains that are
240c8ae9c2dSSudeep Holla	  controlled by firmware that implements the SCMI interface.
241c8ae9c2dSSudeep Holla
242c8ae9c2dSSudeep Holla	  This driver uses SCMI Message Protocol to interact with the
243c8ae9c2dSSudeep Holla	  firmware controlling all the reset signals.
244c8ae9c2dSSudeep Holla
24581c22ad0SPhilipp Zabelconfig RESET_SIMPLE
24618d1909bSBen Dooks	bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
247a6166a4dSChen Wang	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
248c4ada3caSBen Dooks	depends on HAS_IOMEM
24981c22ad0SPhilipp Zabel	help
25081c22ad0SPhilipp Zabel	  This enables a simple reset controller driver for reset lines that
25181c22ad0SPhilipp Zabel	  that can be asserted and deasserted by toggling bits in a contiguous,
25281c22ad0SPhilipp Zabel	  exclusive register space.
25381c22ad0SPhilipp Zabel
2541d7592f8SJoel Stanley	  Currently this driver supports:
2551d7592f8SJoel Stanley	   - Altera SoCFPGAs
2561d7592f8SJoel Stanley	   - ASPEED BMC SoCs
2575ac33eebSAndreas Färber	   - Bitmain BM1880 SoC
2583ab831e5SAndreas Färber	   - Realtek SoCs
2591d7592f8SJoel Stanley	   - RCC reset controller in STM32 MCUs
2601d7592f8SJoel Stanley	   - Allwinner SoCs
261e4d368e0SGreentime Hu	   - SiFive FU740 SoCs
262a6166a4dSChen Wang	   - Sophgo SoCs
2637e0e901dSPhilipp Zabel
264b3ca9888SDinh Nguyenconfig RESET_SOCFPGA
265225c13f0SKrzysztof Kozlowski	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
266225c13f0SKrzysztof Kozlowski	default ARM && ARCH_INTEL_SOCFPGA
267b3ca9888SDinh Nguyen	select RESET_SIMPLE
268b3ca9888SDinh Nguyen	help
269b3ca9888SDinh Nguyen	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
270b3ca9888SDinh Nguyen	  driver gets initialized early during platform init calls.
271b3ca9888SDinh Nguyen
272dbf018beSQin Jianconfig RESET_SUNPLUS
273dbf018beSQin Jian	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
274dbf018beSQin Jian	default ARCH_SUNPLUS
275dbf018beSQin Jian	help
276dbf018beSQin Jian	  This enables the reset driver support for Sunplus SoCs.
277dbf018beSQin Jian	  The reset lines that can be asserted and deasserted by toggling bits
278dbf018beSQin Jian	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
279dbf018beSQin Jian	  which means each register holds 16 reset lines.
280dbf018beSQin Jian
2810ae08419SPhilipp Zabelconfig RESET_SUNXI
2820ae08419SPhilipp Zabel	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
2830ae08419SPhilipp Zabel	default ARCH_SUNXI
284e13c205aSPhilipp Zabel	select RESET_SIMPLE
2850ae08419SPhilipp Zabel	help
2860ae08419SPhilipp Zabel	  This enables the reset driver for Allwinner SoCs.
2870ae08419SPhilipp Zabel
28828df169bSAndrew F. Davisconfig RESET_TI_SCI
28928df169bSAndrew F. Davis	tristate "TI System Control Interface (TI-SCI) reset driver"
29013678f3fSRandy Dunlap	depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
29128df169bSAndrew F. Davis	help
29228df169bSAndrew F. Davis	  This enables the reset driver support over TI System Control Interface
29328df169bSAndrew F. Davis	  available on some new TI's SoCs. If you wish to use reset resources
29428df169bSAndrew F. Davis	  managed by the TI System Controller, say Y here. Otherwise, say N.
29528df169bSAndrew F. Davis
296dd9bf863SSuman Annaconfig RESET_TI_SYSCON
297cc7c2bb1SAndrew F. Davis	tristate "TI SYSCON Reset Driver"
298cc7c2bb1SAndrew F. Davis	depends on HAS_IOMEM
299cc7c2bb1SAndrew F. Davis	select MFD_SYSCON
300cc7c2bb1SAndrew F. Davis	help
301cc7c2bb1SAndrew F. Davis	  This enables the reset driver support for TI devices with
302cc7c2bb1SAndrew F. Davis	  memory-mapped reset registers as part of a syscon device node. If
303cc7c2bb1SAndrew F. Davis	  you wish to use the reset framework for such memory-mapped devices,
304cc7c2bb1SAndrew F. Davis	  say Y here. Otherwise, say N.
305cc7c2bb1SAndrew F. Davis
3068a4e6154SMarco Felschconfig RESET_TI_TPS380X
3078a4e6154SMarco Felsch	tristate "TI TPS380x Reset Driver"
3088a4e6154SMarco Felsch	select GPIOLIB
3098a4e6154SMarco Felsch	help
3108a4e6154SMarco Felsch	  This enables the reset driver support for TI TPS380x devices. If
3118a4e6154SMarco Felsch	  you wish to use the reset framework for such devices, say Y here.
3128a4e6154SMarco Felsch	  Otherwise, say N.
3138a4e6154SMarco Felsch
3145cd3921dSRobert Markoconfig RESET_TN48M_CPLD
3155cd3921dSRobert Marko	tristate "Delta Networks TN48M switch CPLD reset controller"
3165cd3921dSRobert Marko	depends on MFD_TN48M_CPLD || COMPILE_TEST
3175cd3921dSRobert Marko	default MFD_TN48M_CPLD
3185cd3921dSRobert Marko	help
3195cd3921dSRobert Marko	  This enables the reset controller driver for the Delta TN48M CPLD.
3205cd3921dSRobert Marko	  It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
3215cd3921dSRobert Marko	  switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
3225cd3921dSRobert Marko	  Microchip PD69200 PoE PSE controller.
3235cd3921dSRobert Marko
3245cd3921dSRobert Marko	  This driver can also be built as a module. If so, the module will be
3255cd3921dSRobert Marko	  called reset-tn48m.
3265cd3921dSRobert Marko
32754e991b5SMasahiro Yamadaconfig RESET_UNIPHIER
32854e991b5SMasahiro Yamada	tristate "Reset controller driver for UniPhier SoCs"
32954e991b5SMasahiro Yamada	depends on ARCH_UNIPHIER || COMPILE_TEST
33054e991b5SMasahiro Yamada	depends on OF && MFD_SYSCON
33154e991b5SMasahiro Yamada	default ARCH_UNIPHIER
33254e991b5SMasahiro Yamada	help
33354e991b5SMasahiro Yamada	  Support for reset controllers on UniPhier SoCs.
33454e991b5SMasahiro Yamada	  Say Y if you want to control reset signals provided by System Control
33554e991b5SMasahiro Yamada	  block, Media I/O block, Peripheral Block.
33654e991b5SMasahiro Yamada
3373eb8f765SKunihiko Hayashiconfig RESET_UNIPHIER_GLUE
3383eb8f765SKunihiko Hayashi	tristate "Reset driver in glue layer for UniPhier SoCs"
339499fef09SKunihiko Hayashi	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
340499fef09SKunihiko Hayashi	default ARCH_UNIPHIER
341499fef09SKunihiko Hayashi	select RESET_SIMPLE
342499fef09SKunihiko Hayashi	help
3433eb8f765SKunihiko Hayashi	  Support for peripheral core reset included in its own glue layer
3443eb8f765SKunihiko Hayashi	  on UniPhier SoCs. Say Y if you want to control reset signals
3453eb8f765SKunihiko Hayashi	  provided by the glue layer.
346499fef09SKunihiko Hayashi
3476f51b860SPhilipp Zabelconfig RESET_ZYNQ
3486f51b860SPhilipp Zabel	bool "ZYNQ Reset Driver" if COMPILE_TEST
3496f51b860SPhilipp Zabel	default ARCH_ZYNQ
3506f51b860SPhilipp Zabel	help
3516f51b860SPhilipp Zabel	  This enables the reset controller driver for Xilinx Zynq SoCs.
3526f51b860SPhilipp Zabel
3534f6a43adSPhilipp Zabelconfig RESET_ZYNQMP
3544f6a43adSPhilipp Zabel	bool "ZYNQMP Reset Driver" if COMPILE_TEST
3554f6a43adSPhilipp Zabel	default ARCH_ZYNQMP
3564f6a43adSPhilipp Zabel	help
3574f6a43adSPhilipp Zabel	  This enables the reset controller driver for Xilinx ZynqMP SoCs.
3584f6a43adSPhilipp Zabel
35969bfec75SEmil Renner Berthingsource "drivers/reset/starfive/Kconfig"
360e5d76075SStephen Gallimoresource "drivers/reset/sti/Kconfig"
361f59d23c2SChen Fengsource "drivers/reset/hisilicon/Kconfig"
362dc606c52SThierry Redingsource "drivers/reset/tegra/Kconfig"
363998cd463SMasahiro Yamada
364998cd463SMasahiro Yamadaendif
365