1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cardbus bridge setup routines. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/errno.h> 8 #include <linux/ioport.h> 9 #include <linux/pci.h> 10 #include <linux/sizes.h> 11 #include <linux/sprintf.h> 12 #include <linux/types.h> 13 14 #include "pci.h" 15 16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 17 #define CARDBUS_RESERVE_BUSNR 3 18 19 #define DEFAULT_CARDBUS_IO_SIZE SZ_256 20 #define DEFAULT_CARDBUS_MEM_SIZE SZ_64M 21 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 22 static unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 23 static unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 24 25 unsigned long pci_cardbus_resource_alignment(struct resource *res) 26 { 27 if (res->flags & IORESOURCE_IO) 28 return pci_cardbus_io_size; 29 if (res->flags & IORESOURCE_MEM) 30 return pci_cardbus_mem_size; 31 return 0; 32 } 33 34 int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 35 struct list_head *realloc_head) 36 { 37 struct pci_dev *bridge = bus->self; 38 struct resource *b_res; 39 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; 40 u16 ctrl; 41 42 b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; 43 if (resource_assigned(b_res)) 44 goto handle_b_res_1; 45 /* 46 * Reserve some resources for CardBus. We reserve a fixed amount 47 * of bus space for CardBus bridges. 48 */ 49 resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 50 b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 51 if (realloc_head) { 52 b_res->end -= pci_cardbus_io_size; 53 pci_dev_res_add_to_list(realloc_head, bridge, b_res, 54 pci_cardbus_io_size, 55 pci_cardbus_io_size); 56 } 57 58 handle_b_res_1: 59 b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; 60 if (resource_assigned(b_res)) 61 goto handle_b_res_2; 62 resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 63 b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 64 if (realloc_head) { 65 b_res->end -= pci_cardbus_io_size; 66 pci_dev_res_add_to_list(realloc_head, bridge, b_res, 67 pci_cardbus_io_size, 68 pci_cardbus_io_size); 69 } 70 71 handle_b_res_2: 72 /* MEM1 must not be pref MMIO */ 73 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 74 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { 75 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; 76 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 77 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 78 } 79 80 /* Check whether prefetchable memory is supported by this bridge. */ 81 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 82 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 83 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 84 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 85 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 86 } 87 88 b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; 89 if (resource_assigned(b_res)) 90 goto handle_b_res_3; 91 /* 92 * If we have prefetchable memory support, allocate two regions. 93 * Otherwise, allocate one region of twice the size. 94 */ 95 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 96 resource_set_range(b_res, pci_cardbus_mem_size, 97 pci_cardbus_mem_size); 98 b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | 99 IORESOURCE_STARTALIGN; 100 if (realloc_head) { 101 b_res->end -= pci_cardbus_mem_size; 102 pci_dev_res_add_to_list(realloc_head, bridge, b_res, 103 pci_cardbus_mem_size, 104 pci_cardbus_mem_size); 105 } 106 107 /* Reduce that to half */ 108 b_res_3_size = pci_cardbus_mem_size; 109 } 110 111 handle_b_res_3: 112 b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; 113 if (resource_assigned(b_res)) 114 goto handle_done; 115 resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size); 116 b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; 117 if (realloc_head) { 118 b_res->end -= b_res_3_size; 119 pci_dev_res_add_to_list(realloc_head, bridge, b_res, 120 b_res_3_size, pci_cardbus_mem_size); 121 } 122 123 handle_done: 124 return 0; 125 } 126 127 void pci_setup_cardbus_bridge(struct pci_bus *bus) 128 { 129 struct pci_dev *bridge = bus->self; 130 struct resource *res; 131 struct pci_bus_region region; 132 133 pci_info(bridge, "CardBus bridge to %pR\n", 134 &bus->busn_res); 135 136 res = bus->resource[0]; 137 pcibios_resource_to_bus(bridge->bus, ®ion, res); 138 if (resource_assigned(res) && res->flags & IORESOURCE_IO) { 139 /* 140 * The IO resource is allocated a range twice as large as it 141 * would normally need. This allows us to set both IO regs. 142 */ 143 pci_info(bridge, " bridge window %pR\n", res); 144 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 145 region.start); 146 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 147 region.end); 148 } 149 150 res = bus->resource[1]; 151 pcibios_resource_to_bus(bridge->bus, ®ion, res); 152 if (resource_assigned(res) && res->flags & IORESOURCE_IO) { 153 pci_info(bridge, " bridge window %pR\n", res); 154 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 155 region.start); 156 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 157 region.end); 158 } 159 160 res = bus->resource[2]; 161 pcibios_resource_to_bus(bridge->bus, ®ion, res); 162 if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { 163 pci_info(bridge, " bridge window %pR\n", res); 164 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 165 region.start); 166 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 167 region.end); 168 } 169 170 res = bus->resource[3]; 171 pcibios_resource_to_bus(bridge->bus, ®ion, res); 172 if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { 173 pci_info(bridge, " bridge window %pR\n", res); 174 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 175 region.start); 176 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 177 region.end); 178 } 179 } 180 EXPORT_SYMBOL(pci_setup_cardbus_bridge); 181 182 int pci_setup_cardbus(char *str) 183 { 184 if (!strncmp(str, "cbiosize=", 9)) { 185 pci_cardbus_io_size = memparse(str + 9, &str); 186 return 0; 187 } else if (!strncmp(str, "cbmemsize=", 10)) { 188 pci_cardbus_mem_size = memparse(str + 10, &str); 189 return 0; 190 } 191 192 return -ENOENT; 193 } 194 195 int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 196 u32 buses, int max, 197 unsigned int available_buses, int pass) 198 { 199 struct pci_bus *child; 200 bool fixed_buses; 201 u8 fixed_sec, fixed_sub; 202 int next_busnr; 203 u32 i, j = 0; 204 205 /* 206 * We need to assign a number to this bus which we always do in the 207 * second pass. 208 */ 209 if (!pass) { 210 /* 211 * Temporarily disable forwarding of the configuration 212 * cycles on all bridges in this bus segment to avoid 213 * possible conflicts in the second pass between two bridges 214 * programmed with overlapping bus ranges. 215 */ 216 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 217 buses & PCI_SEC_LATENCY_TIMER_MASK); 218 return max; 219 } 220 221 /* Clear errors */ 222 pci_write_config_word(dev, PCI_STATUS, 0xffff); 223 224 /* Read bus numbers from EA Capability (if present) */ 225 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 226 if (fixed_buses) 227 next_busnr = fixed_sec; 228 else 229 next_busnr = max + 1; 230 231 /* 232 * Prevent assigning a bus number that already exists. This can 233 * happen when a bridge is hot-plugged, so in this case we only 234 * re-scan this bus. 235 */ 236 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 237 if (!child) { 238 child = pci_add_new_bus(bus, dev, next_busnr); 239 if (!child) 240 return max; 241 pci_bus_insert_busn_res(child, next_busnr, bus->busn_res.end); 242 } 243 max++; 244 if (available_buses) 245 available_buses--; 246 247 buses = (buses & PCI_SEC_LATENCY_TIMER_MASK) | 248 FIELD_PREP(PCI_PRIMARY_BUS_MASK, child->primary) | 249 FIELD_PREP(PCI_SECONDARY_BUS_MASK, child->busn_res.start) | 250 FIELD_PREP(PCI_SUBORDINATE_BUS_MASK, child->busn_res.end); 251 252 /* 253 * yenta.c forces a secondary latency timer of 176. 254 * Copy that behaviour here. 255 */ 256 buses &= ~PCI_SEC_LATENCY_TIMER_MASK; 257 buses |= FIELD_PREP(PCI_SEC_LATENCY_TIMER_MASK, CARDBUS_LATENCY_TIMER); 258 259 /* We need to blast all three values with a single write */ 260 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 261 262 /* 263 * For CardBus bridges, we leave 4 bus numbers as cards with a 264 * PCI-to-PCI bridge can be inserted later. 265 */ 266 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 267 struct pci_bus *parent = bus; 268 269 if (pci_find_bus(pci_domain_nr(bus), max + i + 1)) 270 break; 271 272 while (parent->parent) { 273 if (!pcibios_assign_all_busses() && 274 (parent->busn_res.end > max) && 275 (parent->busn_res.end <= max + i)) { 276 j = 1; 277 } 278 parent = parent->parent; 279 } 280 if (j) { 281 /* 282 * Often, there are two CardBus bridges -- try to 283 * leave one valid bus number for each one. 284 */ 285 i /= 2; 286 break; 287 } 288 } 289 max += i; 290 291 /* 292 * Set subordinate bus number to its real value. If fixed 293 * subordinate bus number exists from EA capability then use it. 294 */ 295 if (fixed_buses) 296 max = fixed_sub; 297 pci_bus_update_busn_res_end(child, max); 298 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 299 300 scnprintf(child->name, sizeof(child->name), "PCI CardBus %04x:%02x", 301 pci_domain_nr(bus), child->number); 302 303 pbus_validate_busn(child); 304 305 return max; 306 } 307