1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2025 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "mpfs.dtsi" 7#include "mpfs-disco-kit-fabric.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/leds/common.h> 10 11/ { 12 model = "Microchip PolarFire-SoC Discovery Kit"; 13 compatible = "microchip,mpfs-disco-kit-reference-rtl-v2507", 14 "microchip,mpfs-disco-kit", 15 "microchip,mpfs"; 16 17 aliases { 18 ethernet0 = &mac0; 19 serial4 = &mmuart4; 20 }; 21 22 chosen { 23 stdout-path = "serial4:115200n8"; 24 }; 25 26 leds { 27 compatible = "gpio-leds"; 28 29 led-1 { 30 gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; 31 color = <LED_COLOR_ID_AMBER>; 32 label = "led1"; 33 }; 34 35 led-2 { 36 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; 37 color = <LED_COLOR_ID_RED>; 38 label = "led2"; 39 }; 40 41 led-3 { 42 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; 43 color = <LED_COLOR_ID_AMBER>; 44 label = "led3"; 45 }; 46 47 led-4 { 48 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 49 color = <LED_COLOR_ID_RED>; 50 label = "led4"; 51 }; 52 53 led-5 { 54 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; 55 color = <LED_COLOR_ID_AMBER>; 56 label = "led5"; 57 }; 58 59 led-6 { 60 gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; 61 color = <LED_COLOR_ID_RED>; 62 label = "led6"; 63 }; 64 65 led-7 { 66 gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; 67 color = <LED_COLOR_ID_AMBER>; 68 label = "led7"; 69 }; 70 71 led-8 { 72 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 73 color = <LED_COLOR_ID_RED>; 74 label = "led8"; 75 }; 76 }; 77 78 ddrc_cache_lo: memory@80000000 { 79 device_type = "memory"; 80 reg = <0x0 0x80000000 0x0 0x40000000>; 81 }; 82 83 reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 hss_payload: region@bfc00000 { 89 reg = <0x0 0xbfc00000 0x0 0x400000>; 90 no-map; 91 }; 92 }; 93}; 94 95&core_pwm0 { 96 status = "okay"; 97}; 98 99&gpio1 { 100 status = "okay"; 101}; 102 103&gpio2 { 104 status = "okay"; 105}; 106 107&i2c0 { 108 status = "okay"; 109}; 110 111&i2c2 { 112 status = "okay"; 113}; 114 115&ihc { 116 status = "okay"; 117}; 118 119&irqmux { 120 interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, 121 <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, 122 <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, 123 <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, 124 <12 &plic 25>, <13 &plic 26>, 125 126 <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, 127 <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, 128 <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, 129 <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, 130 <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, 131 <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, 132 <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, 133 <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, 134 135 <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, 136 <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, 137 <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, 138 <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, 139 <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, 140 <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, 141 <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, 142 <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, 143 <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, 144 <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, 145 <94 &plic 53>, <95 &plic 53>; 146}; 147 148&mac0 { 149 phy-mode = "sgmii"; 150 phy-handle = <&phy0>; 151 status = "okay"; 152 153 phy0: ethernet-phy@b { 154 reg = <0xb>; 155 }; 156}; 157 158&mbox { 159 status = "okay"; 160}; 161 162&mmc { 163 bus-width = <4>; 164 disable-wp; 165 cap-sd-highspeed; 166 cap-mmc-highspeed; 167 sd-uhs-sdr12; 168 sd-uhs-sdr25; 169 sd-uhs-sdr50; 170 sd-uhs-sdr104; 171 no-1-8-v; 172 status = "okay"; 173}; 174 175&mmuart1 { 176 status = "okay"; 177}; 178 179&mmuart4 { 180 status = "okay"; 181}; 182 183&refclk { 184 clock-frequency = <125000000>; 185}; 186 187&refclk_ccc { 188 clock-frequency = <50000000>; 189}; 190 191&rtc { 192 status = "okay"; 193}; 194 195&spi0 { 196 status = "okay"; 197}; 198 199&spi1 { 200 status = "okay"; 201}; 202 203&syscontroller { 204 status = "okay"; 205}; 206