1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Synopsys DesignWare PCIe interface 8 9maintainers: 10 - Jingoo Han <jingoohan1@gmail.com> 11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 12 13description: | 14 Synopsys DesignWare PCIe host controller 15 16# Please create a separate DT-schema for your DWC PCIe Root Port controller 17# and make sure it's assigned with the vendor-specific compatible string. 18select: 19 properties: 20 compatible: 21 const: snps,dw-pcie 22 required: 23 - compatible 24 25allOf: 26 - $ref: /schemas/pci/pci-bus.yaml# 27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml# 28 - if: 29 not: 30 required: 31 - msi-map 32 then: 33 properties: 34 interrupt-names: 35 contains: 36 const: msi 37 38properties: 39 reg: 40 description: 41 At least DBI reg-space and peripheral devices CFG-space outbound window 42 are required for the normal controller work. iATU memory IO region is 43 also required if the space is unrolled (IP-core version >= 4.80a). 44 minItems: 2 45 maxItems: 5 46 47 reg-names: 48 minItems: 2 49 maxItems: 5 50 items: 51 oneOf: 52 - description: 53 Basic DWC PCIe controller configuration-space accessible over 54 the DBI interface. This memory space is either activated with 55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region 56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible 57 via the PL viewports on the DWC PCIe controllers older than 58 v4.80a. 59 const: dbi 60 - description: 61 Shadow DWC PCIe config-space registers. This space is selected 62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of 63 the PCI-SIG PCIe CFG-space with the shadow registers for some 64 PCI Header space, PCI Standard and Extended Structures. It's 65 mainly relevant for the end-point controller configuration, 66 but still there are some shadow registers available for the 67 Root Port mode too. 68 const: dbi2 69 - description: 70 External Local Bus registers. It's an application-dependent 71 registers normally defined by the platform engineers. The space 72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can 73 be accessed over some platform-specific means (for instance 74 as a part of a system controller). 75 enum: [ elbi, app ] 76 - description: 77 iATU/eDMA registers common for all device functions. It's an 78 unrolled memory space with the internal Address Translation 79 Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1 80 and CS2 = 1. For IP-core releases prior v4.80a, these registers 81 have been programmed via an indirect addressing scheme using a 82 set of viewport CSRs mapped into the PL space. Note iATU is 83 normally mapped to the 0x0 address of this region, while eDMA 84 is available at 0x80000 base address. 85 const: atu 86 - description: 87 Platform-specific eDMA registers. Some platforms may have eDMA 88 CSRs mapped in a non-standard base address. The registers offset 89 can be changed or the MS/LS-bits of the address can be attached 90 in an additional RTL block before the MEM-IO transactions reach 91 the DW PCIe slave interface. 92 const: dma 93 - description: 94 PHY/PCS configuration registers. Some platforms can have the 95 PCS and PHY CSRs accessible over a dedicated memory mapped 96 region, but mainly these registers are indirectly accessible 97 either by means of the embedded PHY viewport schema or by some 98 platform-specific method. 99 const: phy 100 - description: 101 Outbound iATU-capable memory-region which will be used to access 102 the peripheral PCIe devices configuration space. 103 const: config 104 - description: 105 Vendor-specific CSR names. Consider using the generic names above 106 for new bindings. 107 oneOf: 108 - description: See native 'elbi/app' CSR region for details. 109 enum: [ apb, mgmt, link, ulreg, appl ] 110 - description: See native 'atu' CSR region for details. 111 enum: [ atu_dma ] 112 - description: Syscon-related CSR regions. 113 enum: [ smu, mpu ] 114 - description: Tegra234 aperture 115 enum: [ ecam ] 116 allOf: 117 - contains: 118 const: dbi 119 - contains: 120 const: config 121 122 interrupts: 123 description: 124 DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt 125 signal is supposed to be specified for the host controller. 126 minItems: 1 127 maxItems: 26 128 129 interrupt-names: 130 minItems: 1 131 maxItems: 26 132 items: 133 oneOf: 134 - description: 135 Controller request to read or write virtual product data 136 from/to the VPD capability registers. 137 const: vpd 138 - description: 139 Link Equalization Request flag is set in the Link Status 2 140 register (applicable if the corresponding IRQ is enabled in 141 the Link Control 3 register). 142 const: l_eq 143 - description: 144 Indicates that the eDMA Tx/Rx transfer is complete or that an 145 error has occurred on the corresponding channel. eDMA can have 146 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up 147 to 16 IRQ signals all together. Write eDMA channels shall go 148 first in the ordered row as per default edma_int[*] bus setup. 149 pattern: '^dma([0-9]|1[0-5])?$' 150 - description: 151 PCIe protocol correctable error or a Data Path protection 152 correctable error is detected by the automotive/safety 153 feature. 154 const: sft_ce 155 - description: 156 Indicates that the internal safety mechanism has detected an 157 uncorrectable error. 158 const: sft_ue 159 - description: 160 Application-specific IRQ raised depending on the vendor-specific 161 events basis. 162 const: app 163 - description: 164 DSP AXI MSI Interrupt detected. It gets de-asserted when there is 165 no more MSI interrupt pending. The interrupt is relevant to the 166 iMSI-RX - Integrated MSI Receiver (AXI bridge). 167 const: msi 168 - description: 169 Legacy A/B/C/D interrupt signal. Basically it's triggered by 170 receiving a Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message 171 from the downstream device. 172 pattern: "^int(a|b|c|d)$" 173 - description: 174 Error condition detected and a flag is set in the Root Error Status 175 register of the AER capability. It's asserted when the RC 176 internally generated an error or an error message is received by 177 the RC. 178 const: aer 179 - description: 180 PME message is received by the port. That means having the PME 181 status bit set in the Root Status register (the event is 182 supposed to be unmasked in the Root Control register). 183 const: pme 184 - description: 185 Hot-plug event is detected. That is a bit has been set in the 186 Slot Status register and the corresponding event is enabled in 187 the Slot Control register. 188 const: hp 189 - description: 190 Link Autonomous Bandwidth Status flag has been set in the Link 191 Status register (the event is supposed to be unmasked in the 192 Link Control register). 193 const: bw_au 194 - description: 195 Bandwidth Management Status flag has been set in the Link 196 Status register (the event is supposed to be unmasked in the 197 Link Control register). 198 const: bw_mg 199 - description: 200 Combined Legacy A/B/C/D interrupt signal. See "^int(a|b|c|d)$" for 201 details. 202 const: legacy 203 - description: 204 Vendor-specific IRQ names. Consider using the generic names above 205 for new bindings. 206 oneOf: 207 - description: See native "app" IRQ for details 208 enum: [ intr, sys, pmc, msg, err ] 209 210additionalProperties: true 211 212required: 213 - compatible 214 - reg 215 - reg-names 216 217examples: 218 - | 219 pcie@dfc00000 { 220 compatible = "snps,dw-pcie"; 221 device_type = "pci"; 222 reg = <0xdfc00000 0x0001000>, /* IP registers */ 223 <0xd0000000 0x0002000>; /* Configuration space */ 224 reg-names = "dbi", "config"; 225 #address-cells = <3>; 226 #size-cells = <2>; 227 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, 228 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; 229 bus-range = <0x0 0xff>; 230 231 interrupts = <25>, <24>; 232 interrupt-names = "msi", "hp"; 233 #interrupt-cells = <1>; 234 235 reset-gpios = <&port0 0 1>; 236 237 phys = <&pcie_phy>; 238 phy-names = "pcie"; 239 240 num-lanes = <1>; 241 max-link-speed = <3>; 242 }; 243