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Searched refs:readl (Results 1 – 25 of 1570) sorted by relevance

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/linux/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-hw-s5p.c22 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
26 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
59 reg = readl(regs + S5P_JPGMOD); in s5p_jpeg_proc_mode()
74 reg = readl(regs + S5P_JPGMOD); in s5p_jpeg_subsampling_mode()
82 return readl(regs + S5P_JPGMOD) & S5P_SUBSAMPLING_MODE_MASK; in s5p_jpeg_get_subsampling_mode()
89 reg = readl(regs + S5P_JPGDRI_U); in s5p_jpeg_dri()
94 reg = readl(regs + S5P_JPGDRI_L); in s5p_jpeg_dri()
104 reg = readl(regs + S5P_JPG_QTBL); in s5p_jpeg_qtbl()
114 reg = readl(regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_ac()
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-fhctl.c59 readl(regs->reg_hp_en), readl(regs->reg_clk_con), in dump_hw()
60 readl(regs->reg_slope0), readl(regs->reg_slope1)); in dump_hw()
62 readl(regs->reg_cfg), readl(regs->reg_updnlmt), in dump_hw()
63 readl(regs->reg_dds), readl(regs->reg_dvfs), in dump_hw()
64 readl(regs->reg_mon)); in dump_hw()
65 pr_info("pcw<%x>\n", readl(pll->pcw_addr)); in dump_hw()
73 writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
74 writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
75 writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
79 r = readl(regs->reg_cfg); in fhctl_set_ssc_regs()
[all …]
/linux/sound/arm/
H A Dpxa2xx-ac97-lib.c
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac4_dma.c20 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi()
54 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan)); in dwmac4_dma_init_rx_chan()
75 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); in dwmac4_dma_init_tx_chan()
99 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); in dwmac4_dma_init_channel()
115 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan)); in dwmac4_dma_deinit_channel()
128 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); in dwmac410_dma_init_channel()
145 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan)); in dwmac410_dma_deinit_channel()
153 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_init()
171 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_init()
195 readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, channel)); in _dwmac4_dump_dma_regs()
[all …]
H A Ddwxgmac2_dma.c13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
39 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_init()
50 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
67 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
83 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
93 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi()
124 reg_space[i] = readl(ioaddr + i * 4); in dwxgmac2_dma_dump_regs()
130 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode()
152 u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); in dwxgmac2_dma_rx_mode()
[all …]
H A Ddwmac-tegra.c91 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); in tegra_mgbe_resume()
93 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_resume()
120 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
124 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
128 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
133 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
138 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
151 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
155 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
160 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
[all …]
H A Ddwxgmac2_core.c23 tx = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_core_init()
24 rx = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_core_init()
39 value = readl(int_mask) & ~disable; in dwxgmac2_irq_modify()
53 u32 tx = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_set_mac()
54 u32 rx = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_set_mac()
73 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_rx_ipc()
80 return !!(readl(ioaddr + XGMAC_RX_CONFIG) & XGMAC_CONFIG_IPC); in dwxgmac2_rx_ipc()
89 value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue); in dwxgmac2_rx_queue_enable()
105 ctrl2 = readl(ioaddr + XGMAC_RXQ_CTRL2); in dwxgmac2_rx_queue_prio()
106 ctrl3 = readl(ioaddr + XGMAC_RXQ_CTRL3); in dwxgmac2_rx_queue_prio()
[all …]
H A Ddwmac4_core.c48 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init()
70 value = readl(int_mask) & ~disable; in dwmac4_irq_modify()
88 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0); in dwmac4_rx_queue_enable()
107 ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2); in dwmac4_rx_queue_priority()
108 ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3); in dwmac4_rx_queue_priority()
151 value = readl(ioaddr + base_register); in dwmac4_tx_queue_priority()
174 value = readl(ioaddr + GMAC_RXQ_CTRL1); in dwmac4_rx_queue_routing()
197 u32 value = readl(ioaddr + MTL_OPERATION_MODE); in dwmac4_prog_mtl_rx_algorithms()
218 u32 value = readl(ioaddr + MTL_OPERATION_MODE); in dwmac4_prog_mtl_tx_algorithms()
247 u32 value = readl(ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs, in dwmac4_set_mtl_tx_queue_weight()
[all …]
/linux/drivers/scsi/bfa/
H A Dbfa_ioc_ct.c60 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
67 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
74 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_ct_firmware_lock()
87 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
98 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
113 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
120 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_unlock()
134 readl(ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
135 readl(ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
138 readl(ioc->ioc_regs.err_set); in bfa_ioc_ct_notify_fail()
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c26 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
34 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
54 lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_get_lpi_status()
74 irq_status = readl(ioaddr + SXGBE_CORE_INT_STATUS_REG); in sxgbe_core_host_irq_status()
106 high_word = readl(ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n)); in sxgbe_core_get_umac_addr()
107 low_word = readl(ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n)); in sxgbe_core_get_umac_addr()
122 tx_config = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_enable_tx()
134 rx_config = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_enable_rx()
144 return readl(ioaddr + SXGBE_CORE_VERSION_REG); in sxgbe_get_controller_version()
151 return readl(ioaddr + (SXGBE_CORE_HW_FEA_REG(feature_index))); in sxgbe_get_hw_feature()
[all …]
/linux/drivers/net/ethernet/brocade/bna/
H A Dbfa_ioc_ct.c125 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
137 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_ct_firmware_lock()
178 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
194 readl(ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
195 readl(ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
377 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
389 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0); in bfa_ioc_ct2_map_port()
400 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
427 r32 = readl(ioc->ioc_regs.lpu_read_stat); in bfa_ioc_ct2_lpu_read_stat()
450 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
[all …]
/linux/sound/soc/pxa/
H A Dpxa2xx-i2s.c115 readl(i2s_reg_base + SADR); in pxa_i2s_wait()
177 writel(readl(i2s_reg_base + SACR0) | (SACR0_BCKD), i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
179 writel(readl(i2s_reg_base + SACR0) | (SACR0_RFTH(14) | SACR0_TFTH(1)), i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
180 writel(readl(i2s_reg_base + SACR1) | (pxa_i2s.fmt), i2s_reg_base + SACR1); in pxa2xx_i2s_hw_params()
183 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_TFS), i2s_reg_base + SAIMR); in pxa2xx_i2s_hw_params()
185 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_RFS), i2s_reg_base + SAIMR); in pxa2xx_i2s_hw_params()
222 writel(readl(i2s_reg_base + SACR1) & (~SACR1_DRPL), i2s_reg_base + SACR1); in pxa2xx_i2s_trigger()
224 writel(readl(i2s_reg_base + SACR1) & (~SACR1_DREC), i2s_reg_base + SACR1); in pxa2xx_i2s_trigger()
225 writel(readl(i2s_reg_base + SACR0) | (SACR0_ENB), i2s_reg_base + SACR0); in pxa2xx_i2s_trigger()
244 writel(readl(i2s_reg_bas in pxa2xx_i2s_shutdown()
[all...]
/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_mac.c26 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_stop()
32 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_stop()
42 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_start()
48 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_start()
72 ret = read_poll_timeout(readl, reg, reg & MAC_W_MAC_DONE, 1, 200, true, in spl2sw_mac_addr_add()
80 readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0), in spl2sw_mac_addr_add()
82 readl(comm->l2sw_reg_base + L2SW_W_MAC_47_16)), in spl2sw_mac_addr_add()
84 readl(comm->l2sw_reg_base + L2SW_W_MAC_15_0))); in spl2sw_mac_addr_add()
108 ret = read_poll_timeout(readl, reg, reg & MAC_W_MAC_DONE, 1, 200, true, in spl2sw_mac_addr_del()
116 readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0), in spl2sw_mac_addr_del()
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-lite-reg.c25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
30 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
42 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq()
49 u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_get_interrupt_source()
56 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2); in flite_hw_clear_last_capture_end()
77 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_interrupt_mask()
85 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_start()
92 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_stop()
103 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_test_pattern()
144 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_source_format()
[all …]
/linux/sound/soc/sunxi/
H A Dsun8i-adda-pr-regmap.c35 writel(readl(base) | ADDA_PR_RESET, base); in adda_reg_read()
38 writel(readl(base) & ~ADDA_PR_WRITE, base); in adda_reg_read()
41 tmp = readl(base); in adda_reg_read()
47 *val = readl(base) & ADDA_PR_DATA_OUT_MASK; in adda_reg_read()
58 writel(readl(base) | ADDA_PR_RESET, base); in adda_reg_write()
61 tmp = readl(base); in adda_reg_write()
67 tmp = readl(base); in adda_reg_write()
73 writel(readl(base) | ADDA_PR_WRITE, base); in adda_reg_write()
76 writel(readl(base) & ~ADDA_PR_WRITE, base); in adda_reg_write()
/linux/drivers/usb/early/
H A Dehci-dbgp.c82 dbgp_printk(" Debug control: %08x", readl(&ehci_debug->control)); in dbgp_ehci_status()
83 dbgp_printk(" ehci cmd : %08x", readl(&ehci_regs->command)); in dbgp_ehci_status()
85 readl(&ehci_regs->configured_flag)); in dbgp_ehci_status()
86 dbgp_printk(" ehci status : %08x", readl(&ehci_regs->status)); in dbgp_ehci_status()
88 readl(&ehci_regs->port_status[dbgp_phys_port - 1])); in dbgp_ehci_status()
203 pids = readl(&ehci_debug->pids); in dbgp_wait_until_done()
257 lo = readl(&ehci_debug->data03); in dbgp_get_data()
258 hi = readl(&ehci_debug->data47); in dbgp_get_data()
277 pids = readl(&ehci_debug->pids); in dbgp_bulk_write()
280 ctrl = readl(&ehci_debug->control); in dbgp_bulk_write()
[all …]
/linux/drivers/usb/chipidea/
H A Dusbmisc_imx.c213 val = readl(usbmisc->base); in usbmisc_imx25_init()
228 val = readl(usbmisc->base); in usbmisc_imx25_init()
265 val = readl(reg); in usbmisc_imx25_post()
301 val = readl(usbmisc->base) | val; in usbmisc_imx27_init()
303 val = readl(usbmisc->base) & ~val; in usbmisc_imx27_init()
321 val = readl(usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET); in usbmisc_imx53_init()
332 val = readl(reg) | MX53_BM_OVER_CUR_DIS_OTG; in usbmisc_imx53_init()
339 val = readl(reg) | MX53_BM_OVER_CUR_DIS_H1; in usbmisc_imx53_init()
347 val = readl(reg) | MX53_USB_CTRL_1_UH2_ULPI_EN; in usbmisc_imx53_init()
354 val = readl(reg) | MX53_USB_UHx_CTRL_WAKE_UP_EN in usbmisc_imx53_init()
[all …]
/linux/drivers/rtc/
H A Drtc-ftrtc010.c69 sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND); in ftrtc010_rtc_read_time()
70 min = readl(rtc->rtc_base + FTRTC010_RTC_MINUTE); in ftrtc010_rtc_read_time()
71 hour = readl(rtc->rtc_base + FTRTC010_RTC_HOUR); in ftrtc010_rtc_read_time()
72 days = readl(rtc->rtc_base + FTRTC010_RTC_DAYS); in ftrtc010_rtc_read_time()
73 offset = readl(rtc->rtc_base + FTRTC010_RTC_RECORD); in ftrtc010_rtc_read_time()
90 sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND); in ftrtc010_rtc_set_time()
91 min = readl(rtc->rtc_base + FTRTC010_RTC_MINUTE); in ftrtc010_rtc_set_time()
92 hour = readl(rtc->rtc_base + FTRTC010_RTC_HOUR); in ftrtc010_rtc_set_time()
93 day = readl(rtc->rtc_base + FTRTC010_RTC_DAYS); in ftrtc010_rtc_set_time()
170 sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND); in ftrtc010_rtc_probe()
[all …]
H A Drtc-mpfs.c65 ctrl = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
73 u32 val = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
83 (void)readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
91 time = readl(rtcdev->base + DATETIME_LOWER_REG); in mpfs_rtc_readtime()
92 time |= ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32; in mpfs_rtc_readtime()
110 ctrl = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_settime()
115 ret = read_poll_timeout(readl, prog, !(prog & CONTROL_UPLOAD_BIT), 0, UPLOAD_TIMEOUT_US, in mpfs_rtc_settime()
129 u32 mode = readl(rtcdev->base + MODE_REG); in mpfs_rtc_readalarm()
134 time = (u64)readl(rtcdev->base + ALARM_LOWER_REG) << 32; in mpfs_rtc_readalarm()
135 time |= (readl(rtcde in mpfs_rtc_readalarm()
[all...]
/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c609 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_pipe3_set_refclk()
659 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_utmi_set_refclk()
703 reg = readl(reg_base + tune->off); in exynos5_usbdrd_apply_phy_tunes()
715 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); in exynos5_usbdrd_pipe3_init()
721 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_pipe3_init()
733 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
737 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
751 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
758 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
765 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
[all …]
/linux/drivers/clk/mvebu/
H A Dorion.c30 u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & in mv88f5181_get_tclk_freq()
47 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & in mv88f5181_get_cpu_freq()
62 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & in mv88f5181_get_clk_ratio()
100 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) & in mv88f5182_get_tclk_freq()
115 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & in mv88f5182_get_cpu_freq()
130 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & in mv88f5182_get_clk_ratio()
174 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & in mv88f5281_get_cpu_freq()
187 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & in mv88f5281_get_clk_ratio()
225 u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) & in mv88f6183_get_tclk_freq()
240 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) & in mv88f6183_get_cpu_freq()
[all …]
/linux/arch/arm/plat-orion/
H A Dtime.c67 return ~readl(timer_base + TIMER0_VAL_OFF); in orion_read_sched_clock()
89 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event()
101 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
118 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_shutdown()
122 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_shutdown()
145 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_set_periodic()
149 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_set_periodic()
188 return ~readl(timer_base + TIMER0_VAL_OFF); in orion_delay_timer_read()
223 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_time_init()
225 u = readl(timer_base + TIMER_CTRL_OFF); in orion_time_init()
/linux/drivers/phy/spacemit/
H A Dphy-k3-common.c145 val = readl(base + PHY_RESET_CFG); in k3_usb3phy_init_single()
150 val = readl(base + PHY_PU_CK_REG); in k3_usb3phy_init_single()
161 val = readl(base + PHY_PLL_REG2); in k3_usb3phy_init_single()
166 val = readl(base + PHY_MODE_CFG); in k3_usb3phy_init_single()
171 val = readl(base + PHY_ADPT_CFG0); in k3_usb3phy_init_single()
176 val = readl(base + PHY_RXEQ_TIME); in k3_usb3phy_init_single()
194 val = readl(base + PHY_RX_REG_B); in k3_usb3phy_init_single()
253 val = readl(phy_base + PHY_PLL_REG1); in k3_pcie_phy_init()
257 val = readl(phy_base + PHY_PLL_REG2); in k3_pcie_phy_init()
264 val = readl(lane_base + PCIE_RX_REG1); in k3_pcie_phy_init()
[all …]
/linux/drivers/edac/
H A Dversal_edac.c259 regval = readl(ddrmc_base + ECCR0_CE_ADDR_LO_OFFSET); in get_ce_error_info()
262 regval = readl(ddrmc_base + ECCR0_CE_ADDR_HI_OFFSET); in get_ce_error_info()
265 readl(ddrmc_base + ECCR0_CE_DATA_LO_OFFSET), in get_ce_error_info()
266 readl(ddrmc_base + ECCR0_CE_DATA_HI_OFFSET), in get_ce_error_info()
267 readl(ddrmc_base + ECCR0_CE_DATA_PAR_OFFSET)); in get_ce_error_info()
269 regval = readl(ddrmc_base + ECCR1_CE_ADDR_LO_OFFSET); in get_ce_error_info()
270 reghi = readl(ddrmc_base + ECCR1_CE_ADDR_HI_OFFSET); in get_ce_error_info()
272 regval = readl(ddrmc_base + ECCR1_CE_ADDR_HI_OFFSET); in get_ce_error_info()
275 readl(ddrmc_base + ECCR1_CE_DATA_LO_OFFSET), in get_ce_error_info()
276 readl(ddrmc_base + ECCR1_CE_DATA_HI_OFFSET), in get_ce_error_info()
[all …]
/linux/drivers/net/ethernet/agere/
H A Det131x.c758 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_enable()
761 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_enable()
776 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_disable()
779 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_disable()
874 ctl = readl(&adapter->regs->txmac.ctl); in et1310_config_mac_regs2()
875 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
876 cfg2 = readl(&mac->cfg2); in et1310_config_mac_regs2()
877 ifctrl = readl(&mac->if_ctrl); in et1310_config_mac_regs2()
921 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
941 u32 pmcsr = readl(&adapter->regs->global.pm_csr); in et1310_in_phy_coma()
[all …]

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