xref: /linux/sound/soc/sunxi/sun8i-adda-pr-regmap.c (revision 3eb66e91a25497065c5322b1268cbc3953642227)
1*55b407f6SVasily Khoruzhick // SPDX-License-Identifier: GPL-2.0+
2*55b407f6SVasily Khoruzhick /*
3*55b407f6SVasily Khoruzhick  * This driver provides regmap to access to analog part of audio codec
4*55b407f6SVasily Khoruzhick  * found on Allwinner A23, A31s, A33, H3 and A64 Socs
5*55b407f6SVasily Khoruzhick  *
6*55b407f6SVasily Khoruzhick  * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
7*55b407f6SVasily Khoruzhick  * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
8*55b407f6SVasily Khoruzhick  */
9*55b407f6SVasily Khoruzhick 
10*55b407f6SVasily Khoruzhick #include <linux/io.h>
11*55b407f6SVasily Khoruzhick #include <linux/kernel.h>
12*55b407f6SVasily Khoruzhick #include <linux/module.h>
13*55b407f6SVasily Khoruzhick #include <linux/regmap.h>
14*55b407f6SVasily Khoruzhick 
15*55b407f6SVasily Khoruzhick #include "sun8i-adda-pr-regmap.h"
16*55b407f6SVasily Khoruzhick 
17*55b407f6SVasily Khoruzhick /* Analog control register access bits */
18*55b407f6SVasily Khoruzhick #define ADDA_PR			0x0		/* PRCM base + 0x1c0 */
19*55b407f6SVasily Khoruzhick #define ADDA_PR_RESET			BIT(28)
20*55b407f6SVasily Khoruzhick #define ADDA_PR_WRITE			BIT(24)
21*55b407f6SVasily Khoruzhick #define ADDA_PR_ADDR_SHIFT		16
22*55b407f6SVasily Khoruzhick #define ADDA_PR_ADDR_MASK		GENMASK(4, 0)
23*55b407f6SVasily Khoruzhick #define ADDA_PR_DATA_IN_SHIFT		8
24*55b407f6SVasily Khoruzhick #define ADDA_PR_DATA_IN_MASK		GENMASK(7, 0)
25*55b407f6SVasily Khoruzhick #define ADDA_PR_DATA_OUT_SHIFT		0
26*55b407f6SVasily Khoruzhick #define ADDA_PR_DATA_OUT_MASK		GENMASK(7, 0)
27*55b407f6SVasily Khoruzhick 
28*55b407f6SVasily Khoruzhick /* regmap access bits */
adda_reg_read(void * context,unsigned int reg,unsigned int * val)29*55b407f6SVasily Khoruzhick static int adda_reg_read(void *context, unsigned int reg, unsigned int *val)
30*55b407f6SVasily Khoruzhick {
31*55b407f6SVasily Khoruzhick 	void __iomem *base = (void __iomem *)context;
32*55b407f6SVasily Khoruzhick 	u32 tmp;
33*55b407f6SVasily Khoruzhick 
34*55b407f6SVasily Khoruzhick 	/* De-assert reset */
35*55b407f6SVasily Khoruzhick 	writel(readl(base) | ADDA_PR_RESET, base);
36*55b407f6SVasily Khoruzhick 
37*55b407f6SVasily Khoruzhick 	/* Clear write bit */
38*55b407f6SVasily Khoruzhick 	writel(readl(base) & ~ADDA_PR_WRITE, base);
39*55b407f6SVasily Khoruzhick 
40*55b407f6SVasily Khoruzhick 	/* Set register address */
41*55b407f6SVasily Khoruzhick 	tmp = readl(base);
42*55b407f6SVasily Khoruzhick 	tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
43*55b407f6SVasily Khoruzhick 	tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
44*55b407f6SVasily Khoruzhick 	writel(tmp, base);
45*55b407f6SVasily Khoruzhick 
46*55b407f6SVasily Khoruzhick 	/* Read back value */
47*55b407f6SVasily Khoruzhick 	*val = readl(base) & ADDA_PR_DATA_OUT_MASK;
48*55b407f6SVasily Khoruzhick 
49*55b407f6SVasily Khoruzhick 	return 0;
50*55b407f6SVasily Khoruzhick }
51*55b407f6SVasily Khoruzhick 
adda_reg_write(void * context,unsigned int reg,unsigned int val)52*55b407f6SVasily Khoruzhick static int adda_reg_write(void *context, unsigned int reg, unsigned int val)
53*55b407f6SVasily Khoruzhick {
54*55b407f6SVasily Khoruzhick 	void __iomem *base = (void __iomem *)context;
55*55b407f6SVasily Khoruzhick 	u32 tmp;
56*55b407f6SVasily Khoruzhick 
57*55b407f6SVasily Khoruzhick 	/* De-assert reset */
58*55b407f6SVasily Khoruzhick 	writel(readl(base) | ADDA_PR_RESET, base);
59*55b407f6SVasily Khoruzhick 
60*55b407f6SVasily Khoruzhick 	/* Set register address */
61*55b407f6SVasily Khoruzhick 	tmp = readl(base);
62*55b407f6SVasily Khoruzhick 	tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
63*55b407f6SVasily Khoruzhick 	tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
64*55b407f6SVasily Khoruzhick 	writel(tmp, base);
65*55b407f6SVasily Khoruzhick 
66*55b407f6SVasily Khoruzhick 	/* Set data to write */
67*55b407f6SVasily Khoruzhick 	tmp = readl(base);
68*55b407f6SVasily Khoruzhick 	tmp &= ~(ADDA_PR_DATA_IN_MASK << ADDA_PR_DATA_IN_SHIFT);
69*55b407f6SVasily Khoruzhick 	tmp |= (val & ADDA_PR_DATA_IN_MASK) << ADDA_PR_DATA_IN_SHIFT;
70*55b407f6SVasily Khoruzhick 	writel(tmp, base);
71*55b407f6SVasily Khoruzhick 
72*55b407f6SVasily Khoruzhick 	/* Set write bit to signal a write */
73*55b407f6SVasily Khoruzhick 	writel(readl(base) | ADDA_PR_WRITE, base);
74*55b407f6SVasily Khoruzhick 
75*55b407f6SVasily Khoruzhick 	/* Clear write bit */
76*55b407f6SVasily Khoruzhick 	writel(readl(base) & ~ADDA_PR_WRITE, base);
77*55b407f6SVasily Khoruzhick 
78*55b407f6SVasily Khoruzhick 	return 0;
79*55b407f6SVasily Khoruzhick }
80*55b407f6SVasily Khoruzhick 
81*55b407f6SVasily Khoruzhick static const struct regmap_config adda_pr_regmap_cfg = {
82*55b407f6SVasily Khoruzhick 	.name		= "adda-pr",
83*55b407f6SVasily Khoruzhick 	.reg_bits	= 5,
84*55b407f6SVasily Khoruzhick 	.reg_stride	= 1,
85*55b407f6SVasily Khoruzhick 	.val_bits	= 8,
86*55b407f6SVasily Khoruzhick 	.reg_read	= adda_reg_read,
87*55b407f6SVasily Khoruzhick 	.reg_write	= adda_reg_write,
88*55b407f6SVasily Khoruzhick 	.fast_io	= true,
89*55b407f6SVasily Khoruzhick 	.max_register	= 31,
90*55b407f6SVasily Khoruzhick };
91*55b407f6SVasily Khoruzhick 
sun8i_adda_pr_regmap_init(struct device * dev,void __iomem * base)92*55b407f6SVasily Khoruzhick struct regmap *sun8i_adda_pr_regmap_init(struct device *dev,
93*55b407f6SVasily Khoruzhick 					 void __iomem *base)
94*55b407f6SVasily Khoruzhick {
95*55b407f6SVasily Khoruzhick 	return devm_regmap_init(dev, NULL, base, &adda_pr_regmap_cfg);
96*55b407f6SVasily Khoruzhick }
97*55b407f6SVasily Khoruzhick EXPORT_SYMBOL_GPL(sun8i_adda_pr_regmap_init);
98*55b407f6SVasily Khoruzhick 
99*55b407f6SVasily Khoruzhick MODULE_DESCRIPTION("Allwinner analog audio codec regmap driver");
100*55b407f6SVasily Khoruzhick MODULE_AUTHOR("Vasily Khoruzhick <anarsoul@gmail.com>");
101*55b407f6SVasily Khoruzhick MODULE_LICENSE("GPL");
102*55b407f6SVasily Khoruzhick MODULE_ALIAS("platform:sunxi-adda-pr");
103