| /linux/drivers/irqchip/ |
| H A D | qcom-pdc.c | 42 u32 pin_base; member
47 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
256 if (pin >= pdc_region[i].pin_base && in get_pin_region()
257 pin < pdc_region[i].pin_base + pdc_region[i].cnt) in get_pin_region()
330 &pdc_region[n].pin_base); in pdc_setup_pin_mapping()
345 __pdc_enable_intr(i + pdc_region[n].pin_base, 0); in pdc_setup_pin_mapping()
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| /linux/drivers/gpio/ |
| H A D | gpio-tangier.h | 54 unsigned int pin_base; member
61 .pin_base = (pstart), \
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| H A D | gpio-tangier.c | 404 range->pin_base, in tng_gpio_add_pin_ranges()
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| H A D | gpio-rockchip.c | 585 gc->base = bank->pin_base; in rockchip_gpiolib_register()
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| /linux/drivers/pinctrl/ |
| H A D | pinctrl-equilibrium.c | 286 if (pin >= bank->pin_base && in find_pinbank_via_pin()
287 (pin - bank->pin_base) < bank->nr_pins) in find_pinbank_via_pin()
316 offset = pin - bank->pin_base; in eqbr_set_pin_mux()
321 pin, bank->pin_base, bank->aval_pinmap); in eqbr_set_pin_mux()
413 offset = pin - bank->pin_base; in eqbr_pinconf_get()
418 pin, bank->pin_base, bank->aval_pinmap); in eqbr_pinconf_get()
443 bank->pin_base, pin); in eqbr_pinconf_get()
484 offset = pin - bank->pin_base; in eqbr_pinconf_set()
512 bank->pin_base, pin); in eqbr_pinconf_set()
854 bank->pin_base = spec.args[1]; in pinbank_init()
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| H A D | core.c | 292 return range->pin_base + pin; in gpio_to_pin()
499 } else if (pin >= range->pin_base && in pinctrl_find_gpio_range_from_pin_nolock()
500 pin < range->pin_base + range->npins) in pinctrl_find_gpio_range_from_pin_nolock()
1728 } else if ((pin >= range->pin_base) && in pinctrl_pins_show()
1729 (pin < (range->pin_base + range->npins))) { in pinctrl_pins_show()
1731 range->base + (pin - range->pin_base); in pinctrl_pins_show()
1834 range->pin_base, in pinctrl_gpioranges_show()
1835 (range->pin_base + range->npins - 1)); in pinctrl_gpioranges_show()
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| H A D | pinctrl-rockchip.c | 339 while (pin >= (b->pin_base + b->nr_pins)) in pin_to_bank()
3529 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
3539 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
3556 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); in rockchip_pmx_gpio_request_enable()
3645 pin - bank->pin_base, in rockchip_pinconf_set()
3652 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3667 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3673 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3678 rc = gpio->direction_output(gpio, pin - bank->pin_base, in rockchip_pinconf_set()
3684 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
[all …]
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| H A D | pinctrl-pistachio.c | 98 unsigned int pin_base; member
987 gpio_disable(gpiochip_get_data(range->gc), pg->pin - range->pin_base); in pistachio_pinmux_enable()
1324 .pin_base = _pin_base, \
1434 bank->pin_base, bank->npins); in pistachio_gpio_register()
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| H A D | pinctrl-mlxbf3.c | 39 .pin_base = _pinbase, \
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| H A D | pinctrl-amdisp.c | 159 grange->pin_base = 0; in amdisp_gpiochip_add()
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| H A D | pinctrl-rockchip.h | 329 u32 pin_base; member
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| /linux/drivers/pinctrl/sunxi/ |
| H A D | pinctrl-sunxi.c | 589 pin -= pctl->desc->pin_base; in sunxi_pconf_get()
648 pin -= pctl->desc->pin_base; in sunxi_pconf_set()
742 pin -= pctl->desc->pin_base; in sunxi_pinctrl_set_io_bias_cfg()
829 pin -= pctl->desc->pin_base; in sunxi_pmx_set()
888 unsigned short bank_offset = bank - pctl->desc->pin_base / in sunxi_pmx_request()
934 unsigned short bank_offset = bank - pctl->desc->pin_base / in sunxi_pmx_free()
1070 unsigned pinnum = pctl->desc->pin_base + offset; in sunxi_pinctrl_gpio_to_irq()
1100 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); in sunxi_pinctrl_irq_request_resources()
1118 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); in sunxi_pinctrl_irq_release_resources()
1271 pin = pctl->desc->pin_base + base + intspec[1]; in sunxi_pinctrl_irq_of_xlate()
[all …]
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| H A D | pinctrl-sun50i-h616-r.c | 33 .pin_base = PL_BASE,
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| H A D | pinctrl-sun8i-h3-r.c | 83 .pin_base = PL_BASE,
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| H A D | pinctrl-sun8i-a23-r.c | 92 .pin_base = PL_BASE,
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| H A D | pinctrl-sun50i-a100-r.c | 82 .pin_base = PL_BASE,
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| H A D | pinctrl-sun8i-a83t-r.c | 104 .pin_base = PL_BASE,
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| H A D | pinctrl-sun50i-a64-r.c | 101 .pin_base = PL_BASE,
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| H A D | pinctrl-sun50i-h6-r.c | 106 .pin_base = PL_BASE,
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| H A D | pinctrl-sun6i-a31-r.c | 105 .pin_base = PL_BASE,
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| /linux/drivers/pinctrl/starfive/ |
| H A D | pinctrl-starfive-jh7100.c | 219 return pin - sfp->gpios.pin_base; in starfive_pin_to_gpio()
225 return sfp->gpios.pin_base + gpio; in starfive_gpio_to_pin()
1279 sfp->gpios.pin_base = PAD_INVALID_GPIO; in starfive_probe()
1282 sfp->gpios.pin_base = PAD_GPIO(0); in starfive_probe()
1285 sfp->gpios.pin_base = PAD_FUNC_SHARE(72); in starfive_probe()
1288 sfp->gpios.pin_base = PAD_FUNC_SHARE(70); in starfive_probe()
1291 sfp->gpios.pin_base = PAD_FUNC_SHARE(0); in starfive_probe()
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| /linux/drivers/pinctrl/meson/ |
| H A D | pinctrl-amlogic-a4.c | 91 unsigned int pin_base; member
166 shift = ((pin - range->pin_base) << 2) + *offset; in aml_pmx_calc_reg_and_offset()
284 *bit = (pin - range->pin_base) * aml_bit_strides[reg_type] in aml_calc_reg_and_bit()
1042 bank->pin_base = bank->bank_id << 8; in aml_gpiolib_register_bank()
1095 k = info->banks[bank].pin_base; in aml_pctl_probe_dt()
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| /linux/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-mvebu.h | 188 .pin_base = _pinbase, \
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| /linux/drivers/pinctrl/renesas/ |
| H A D | pinctrl-rza2.c | 272 priv->gpio_range.pin_base = priv->gpio_range.base = 0; in rza2_gpio_register()
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| /linux/drivers/pinctrl/uniphier/ |
| H A D | pinctrl-uniphier-core.c | 681 gpio_offset = offset - range->pin_base; in uniphier_pmx_gpio_request_enable()
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