1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Intel Tangier GPIO functions 4 * 5 * Copyright (c) 2016, 2021, 2023 Intel Corporation. 6 * 7 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 * Pandith N <pandith.n@intel.com> 9 * Raag Jadav <raag.jadav@intel.com> 10 */ 11 12 #ifndef _GPIO_TANGIER_H_ 13 #define _GPIO_TANGIER_H_ 14 15 #include <linux/gpio/driver.h> 16 #include <linux/pm.h> 17 #include <linux/spinlock_types.h> 18 #include <linux/types.h> 19 20 struct device; 21 22 struct tng_gpio_context; 23 24 /* Elkhart Lake specific wake registers */ 25 #define GWMR_EHL 0x100 /* Wake mask */ 26 #define GWSR_EHL 0x118 /* Wake source */ 27 #define GSIR_EHL 0x130 /* Secure input */ 28 29 /* Merrifield specific wake registers */ 30 #define GWMR_MRFLD 0x400 /* Wake mask */ 31 #define GWSR_MRFLD 0x418 /* Wake source */ 32 #define GSIR_MRFLD 0xc00 /* Secure input */ 33 34 /** 35 * struct tng_wake_regs - Platform specific wake registers 36 * @gwmr: Wake mask 37 * @gwsr: Wake source 38 * @gsir: Secure input 39 */ 40 struct tng_wake_regs { 41 u32 gwmr; 42 u32 gwsr; 43 u32 gsir; 44 }; 45 46 /** 47 * struct tng_gpio_pinrange - Map pin numbers to gpio numbers 48 * @gpio_base: Starting GPIO number of this range 49 * @pin_base: Starting pin number of this range 50 * @npins: Number of pins in this range 51 */ 52 struct tng_gpio_pinrange { 53 unsigned int gpio_base; 54 unsigned int pin_base; 55 unsigned int npins; 56 }; 57 58 #define GPIO_PINRANGE(gstart, gend, pstart) \ 59 (struct tng_gpio_pinrange) { \ 60 .gpio_base = (gstart), \ 61 .pin_base = (pstart), \ 62 .npins = (gend) - (gstart) + 1, \ 63 } 64 65 /** 66 * struct tng_gpio_pin_info - Platform specific pinout information 67 * @pin_ranges: Pin to GPIO mapping 68 * @nranges: Number of pin ranges 69 * @name: Respective pinctrl device name 70 */ 71 struct tng_gpio_pin_info { 72 const struct tng_gpio_pinrange *pin_ranges; 73 unsigned int nranges; 74 const char *name; 75 }; 76 77 /** 78 * struct tng_gpio_info - Platform specific GPIO and IRQ information 79 * @base: GPIO base to start numbering with 80 * @ngpio: Amount of GPIOs supported by the controller 81 * @first: First IRQ to start numbering with 82 */ 83 struct tng_gpio_info { 84 int base; 85 u16 ngpio; 86 unsigned int first; 87 }; 88 89 /** 90 * struct tng_gpio - Platform specific private data 91 * @chip: Instance of the struct gpio_chip 92 * @reg_base: Base address of MMIO registers 93 * @irq: Interrupt for the GPIO device 94 * @lock: Synchronization lock to prevent I/O race conditions 95 * @dev: The GPIO device 96 * @ctx: Context to be saved during suspend-resume 97 * @wake_regs: Platform specific wake registers 98 * @pin_info: Platform specific pinout information 99 * @info: Platform specific GPIO and IRQ information 100 */ 101 struct tng_gpio { 102 struct gpio_chip chip; 103 void __iomem *reg_base; 104 int irq; 105 raw_spinlock_t lock; 106 struct device *dev; 107 struct tng_gpio_context *ctx; 108 struct tng_wake_regs wake_regs; 109 struct tng_gpio_pin_info pin_info; 110 struct tng_gpio_info info; 111 }; 112 113 int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio); 114 115 extern const struct dev_pm_ops tng_gpio_pm_ops; 116 117 #endif /* _GPIO_TANGIER_H_ */ 118