1c0f84760SKrzysztof Kozlowski // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2d11f9328SAsmaa Mnebhi /* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */
3d11f9328SAsmaa Mnebhi
4d11f9328SAsmaa Mnebhi #include <linux/bitfield.h>
5d11f9328SAsmaa Mnebhi #include <linux/bitops.h>
6d11f9328SAsmaa Mnebhi #include <linux/err.h>
7d11f9328SAsmaa Mnebhi #include <linux/io.h>
8d11f9328SAsmaa Mnebhi #include <linux/module.h>
9d11f9328SAsmaa Mnebhi #include <linux/mod_devicetable.h>
10d11f9328SAsmaa Mnebhi #include <linux/platform_device.h>
11d11f9328SAsmaa Mnebhi #include <linux/types.h>
12d11f9328SAsmaa Mnebhi
13d11f9328SAsmaa Mnebhi #include <linux/pinctrl/pinctrl.h>
14d11f9328SAsmaa Mnebhi #include <linux/pinctrl/pinmux.h>
15d11f9328SAsmaa Mnebhi
16d11f9328SAsmaa Mnebhi #define MLXBF3_NGPIOS_GPIO0 32
17d11f9328SAsmaa Mnebhi #define MLXBF3_MAX_GPIO_PINS 56
18d11f9328SAsmaa Mnebhi
19d11f9328SAsmaa Mnebhi enum {
20d11f9328SAsmaa Mnebhi MLXBF3_GPIO_HW_MODE,
21d11f9328SAsmaa Mnebhi MLXBF3_GPIO_SW_MODE,
22d11f9328SAsmaa Mnebhi };
23d11f9328SAsmaa Mnebhi
24d11f9328SAsmaa Mnebhi struct mlxbf3_pinctrl {
25d11f9328SAsmaa Mnebhi void __iomem *fw_ctrl_set0;
26d11f9328SAsmaa Mnebhi void __iomem *fw_ctrl_clr0;
27d11f9328SAsmaa Mnebhi void __iomem *fw_ctrl_set1;
28d11f9328SAsmaa Mnebhi void __iomem *fw_ctrl_clr1;
29d11f9328SAsmaa Mnebhi struct device *dev;
30d11f9328SAsmaa Mnebhi struct pinctrl_dev *pctl;
31d11f9328SAsmaa Mnebhi struct pinctrl_gpio_range gpio_range;
32d11f9328SAsmaa Mnebhi };
33d11f9328SAsmaa Mnebhi
34d11f9328SAsmaa Mnebhi #define MLXBF3_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
35d11f9328SAsmaa Mnebhi { \
36d11f9328SAsmaa Mnebhi .name = "mlxbf3_gpio_range", \
37d11f9328SAsmaa Mnebhi .id = _id, \
38d11f9328SAsmaa Mnebhi .base = _gpiobase, \
39d11f9328SAsmaa Mnebhi .pin_base = _pinbase, \
40d11f9328SAsmaa Mnebhi .npins = _npins, \
41d11f9328SAsmaa Mnebhi }
42d11f9328SAsmaa Mnebhi
43d11f9328SAsmaa Mnebhi static struct pinctrl_gpio_range mlxbf3_pinctrl_gpio_ranges[] = {
44d11f9328SAsmaa Mnebhi MLXBF3_GPIO_RANGE(0, 0, 480, 32),
45d11f9328SAsmaa Mnebhi MLXBF3_GPIO_RANGE(1, 32, 456, 24),
46d11f9328SAsmaa Mnebhi };
47d11f9328SAsmaa Mnebhi
48d11f9328SAsmaa Mnebhi static const struct pinctrl_pin_desc mlxbf3_pins[] = {
49d11f9328SAsmaa Mnebhi PINCTRL_PIN(0, "gpio0"),
50d11f9328SAsmaa Mnebhi PINCTRL_PIN(1, "gpio1"),
51d11f9328SAsmaa Mnebhi PINCTRL_PIN(2, "gpio2"),
52d11f9328SAsmaa Mnebhi PINCTRL_PIN(3, "gpio3"),
53d11f9328SAsmaa Mnebhi PINCTRL_PIN(4, "gpio4"),
54d11f9328SAsmaa Mnebhi PINCTRL_PIN(5, "gpio5"),
55d11f9328SAsmaa Mnebhi PINCTRL_PIN(6, "gpio6"),
56d11f9328SAsmaa Mnebhi PINCTRL_PIN(7, "gpio7"),
57d11f9328SAsmaa Mnebhi PINCTRL_PIN(8, "gpio8"),
58d11f9328SAsmaa Mnebhi PINCTRL_PIN(9, "gpio9"),
59d11f9328SAsmaa Mnebhi PINCTRL_PIN(10, "gpio10"),
60d11f9328SAsmaa Mnebhi PINCTRL_PIN(11, "gpio11"),
61d11f9328SAsmaa Mnebhi PINCTRL_PIN(12, "gpio12"),
62d11f9328SAsmaa Mnebhi PINCTRL_PIN(13, "gpio13"),
63d11f9328SAsmaa Mnebhi PINCTRL_PIN(14, "gpio14"),
64d11f9328SAsmaa Mnebhi PINCTRL_PIN(15, "gpio15"),
65d11f9328SAsmaa Mnebhi PINCTRL_PIN(16, "gpio16"),
66d11f9328SAsmaa Mnebhi PINCTRL_PIN(17, "gpio17"),
67d11f9328SAsmaa Mnebhi PINCTRL_PIN(18, "gpio18"),
68d11f9328SAsmaa Mnebhi PINCTRL_PIN(19, "gpio19"),
69d11f9328SAsmaa Mnebhi PINCTRL_PIN(20, "gpio20"),
70d11f9328SAsmaa Mnebhi PINCTRL_PIN(21, "gpio21"),
71d11f9328SAsmaa Mnebhi PINCTRL_PIN(22, "gpio22"),
72d11f9328SAsmaa Mnebhi PINCTRL_PIN(23, "gpio23"),
73d11f9328SAsmaa Mnebhi PINCTRL_PIN(24, "gpio24"),
74d11f9328SAsmaa Mnebhi PINCTRL_PIN(25, "gpio25"),
75d11f9328SAsmaa Mnebhi PINCTRL_PIN(26, "gpio26"),
76d11f9328SAsmaa Mnebhi PINCTRL_PIN(27, "gpio27"),
77d11f9328SAsmaa Mnebhi PINCTRL_PIN(28, "gpio28"),
78d11f9328SAsmaa Mnebhi PINCTRL_PIN(29, "gpio29"),
79d11f9328SAsmaa Mnebhi PINCTRL_PIN(30, "gpio30"),
80d11f9328SAsmaa Mnebhi PINCTRL_PIN(31, "gpio31"),
81d11f9328SAsmaa Mnebhi PINCTRL_PIN(32, "gpio32"),
82d11f9328SAsmaa Mnebhi PINCTRL_PIN(33, "gpio33"),
83d11f9328SAsmaa Mnebhi PINCTRL_PIN(34, "gpio34"),
84d11f9328SAsmaa Mnebhi PINCTRL_PIN(35, "gpio35"),
85d11f9328SAsmaa Mnebhi PINCTRL_PIN(36, "gpio36"),
86d11f9328SAsmaa Mnebhi PINCTRL_PIN(37, "gpio37"),
87d11f9328SAsmaa Mnebhi PINCTRL_PIN(38, "gpio38"),
88d11f9328SAsmaa Mnebhi PINCTRL_PIN(39, "gpio39"),
89d11f9328SAsmaa Mnebhi PINCTRL_PIN(40, "gpio40"),
90d11f9328SAsmaa Mnebhi PINCTRL_PIN(41, "gpio41"),
91d11f9328SAsmaa Mnebhi PINCTRL_PIN(42, "gpio42"),
92d11f9328SAsmaa Mnebhi PINCTRL_PIN(43, "gpio43"),
93d11f9328SAsmaa Mnebhi PINCTRL_PIN(44, "gpio44"),
94d11f9328SAsmaa Mnebhi PINCTRL_PIN(45, "gpio45"),
95d11f9328SAsmaa Mnebhi PINCTRL_PIN(46, "gpio46"),
96d11f9328SAsmaa Mnebhi PINCTRL_PIN(47, "gpio47"),
97d11f9328SAsmaa Mnebhi PINCTRL_PIN(48, "gpio48"),
98d11f9328SAsmaa Mnebhi PINCTRL_PIN(49, "gpio49"),
99d11f9328SAsmaa Mnebhi PINCTRL_PIN(50, "gpio50"),
100d11f9328SAsmaa Mnebhi PINCTRL_PIN(51, "gpio51"),
101d11f9328SAsmaa Mnebhi PINCTRL_PIN(52, "gpio52"),
102d11f9328SAsmaa Mnebhi PINCTRL_PIN(53, "gpio53"),
103d11f9328SAsmaa Mnebhi PINCTRL_PIN(54, "gpio54"),
104d11f9328SAsmaa Mnebhi PINCTRL_PIN(55, "gpio55"),
105d11f9328SAsmaa Mnebhi };
106d11f9328SAsmaa Mnebhi
107d11f9328SAsmaa Mnebhi /*
108d11f9328SAsmaa Mnebhi * All single-pin functions can be mapped to any GPIO, however pinmux applies
109d11f9328SAsmaa Mnebhi * functions to pin groups and only those groups declared as supporting that
110d11f9328SAsmaa Mnebhi * function. To make this work we must put each pin in its own dummy group so
111d11f9328SAsmaa Mnebhi * that the functions can be described as applying to all pins.
112d11f9328SAsmaa Mnebhi * We use the same name as in the datasheet.
113d11f9328SAsmaa Mnebhi */
114d11f9328SAsmaa Mnebhi static const char * const mlxbf3_pinctrl_single_group_names[] = {
115d11f9328SAsmaa Mnebhi "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
116d11f9328SAsmaa Mnebhi "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
117d11f9328SAsmaa Mnebhi "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
118d11f9328SAsmaa Mnebhi "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
119d11f9328SAsmaa Mnebhi "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
120d11f9328SAsmaa Mnebhi "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
121d11f9328SAsmaa Mnebhi "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55",
122d11f9328SAsmaa Mnebhi };
123d11f9328SAsmaa Mnebhi
mlxbf3_get_groups_count(struct pinctrl_dev * pctldev)124d11f9328SAsmaa Mnebhi static int mlxbf3_get_groups_count(struct pinctrl_dev *pctldev)
125d11f9328SAsmaa Mnebhi {
126d11f9328SAsmaa Mnebhi /* Number single-pin groups */
127d11f9328SAsmaa Mnebhi return MLXBF3_MAX_GPIO_PINS;
128d11f9328SAsmaa Mnebhi }
129d11f9328SAsmaa Mnebhi
mlxbf3_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)130d11f9328SAsmaa Mnebhi static const char *mlxbf3_get_group_name(struct pinctrl_dev *pctldev,
131d11f9328SAsmaa Mnebhi unsigned int selector)
132d11f9328SAsmaa Mnebhi {
133d11f9328SAsmaa Mnebhi return mlxbf3_pinctrl_single_group_names[selector];
134d11f9328SAsmaa Mnebhi }
135d11f9328SAsmaa Mnebhi
mlxbf3_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)136d11f9328SAsmaa Mnebhi static int mlxbf3_get_group_pins(struct pinctrl_dev *pctldev,
137d11f9328SAsmaa Mnebhi unsigned int selector,
138d11f9328SAsmaa Mnebhi const unsigned int **pins,
139d11f9328SAsmaa Mnebhi unsigned int *num_pins)
140d11f9328SAsmaa Mnebhi {
141d11f9328SAsmaa Mnebhi /* return the dummy group for a single pin */
142d11f9328SAsmaa Mnebhi *pins = &selector;
143d11f9328SAsmaa Mnebhi *num_pins = 1;
144d11f9328SAsmaa Mnebhi
145d11f9328SAsmaa Mnebhi return 0;
146d11f9328SAsmaa Mnebhi }
147d11f9328SAsmaa Mnebhi
148d11f9328SAsmaa Mnebhi static const struct pinctrl_ops mlxbf3_pinctrl_group_ops = {
149d11f9328SAsmaa Mnebhi .get_groups_count = mlxbf3_get_groups_count,
150d11f9328SAsmaa Mnebhi .get_group_name = mlxbf3_get_group_name,
151d11f9328SAsmaa Mnebhi .get_group_pins = mlxbf3_get_group_pins,
152d11f9328SAsmaa Mnebhi };
153d11f9328SAsmaa Mnebhi
154d11f9328SAsmaa Mnebhi /*
155d11f9328SAsmaa Mnebhi * Only 2 functions are supported and they apply to all pins:
156d11f9328SAsmaa Mnebhi * 1) Default hardware functionality
157d11f9328SAsmaa Mnebhi * 2) Software controlled GPIO
158d11f9328SAsmaa Mnebhi */
159d11f9328SAsmaa Mnebhi static const char * const mlxbf3_gpiofunc_group_names[] = { "swctrl" };
160d11f9328SAsmaa Mnebhi static const char * const mlxbf3_hwfunc_group_names[] = { "hwctrl" };
161d11f9328SAsmaa Mnebhi
162743d3336STom Rix static struct pinfunction mlxbf3_pmx_funcs[] = {
163d11f9328SAsmaa Mnebhi PINCTRL_PINFUNCTION("hwfunc", mlxbf3_hwfunc_group_names, 1),
164d11f9328SAsmaa Mnebhi PINCTRL_PINFUNCTION("gpiofunc", mlxbf3_gpiofunc_group_names, 1),
165d11f9328SAsmaa Mnebhi };
166d11f9328SAsmaa Mnebhi
mlxbf3_pmx_get_funcs_count(struct pinctrl_dev * pctldev)167d11f9328SAsmaa Mnebhi static int mlxbf3_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
168d11f9328SAsmaa Mnebhi {
169d11f9328SAsmaa Mnebhi return ARRAY_SIZE(mlxbf3_pmx_funcs);
170d11f9328SAsmaa Mnebhi }
171d11f9328SAsmaa Mnebhi
mlxbf3_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned int selector)172d11f9328SAsmaa Mnebhi static const char *mlxbf3_pmx_get_func_name(struct pinctrl_dev *pctldev,
173d11f9328SAsmaa Mnebhi unsigned int selector)
174d11f9328SAsmaa Mnebhi {
175d11f9328SAsmaa Mnebhi return mlxbf3_pmx_funcs[selector].name;
176d11f9328SAsmaa Mnebhi }
177d11f9328SAsmaa Mnebhi
mlxbf3_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)178d11f9328SAsmaa Mnebhi static int mlxbf3_pmx_get_groups(struct pinctrl_dev *pctldev,
179d11f9328SAsmaa Mnebhi unsigned int selector,
180d11f9328SAsmaa Mnebhi const char * const **groups,
181d11f9328SAsmaa Mnebhi unsigned int * const num_groups)
182d11f9328SAsmaa Mnebhi {
183d11f9328SAsmaa Mnebhi *groups = mlxbf3_pmx_funcs[selector].groups;
184d11f9328SAsmaa Mnebhi *num_groups = MLXBF3_MAX_GPIO_PINS;
185d11f9328SAsmaa Mnebhi
186d11f9328SAsmaa Mnebhi return 0;
187d11f9328SAsmaa Mnebhi }
188d11f9328SAsmaa Mnebhi
mlxbf3_pmx_set(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)189d11f9328SAsmaa Mnebhi static int mlxbf3_pmx_set(struct pinctrl_dev *pctldev,
190d11f9328SAsmaa Mnebhi unsigned int selector,
191d11f9328SAsmaa Mnebhi unsigned int group)
192d11f9328SAsmaa Mnebhi {
193d11f9328SAsmaa Mnebhi struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
194d11f9328SAsmaa Mnebhi
195d11f9328SAsmaa Mnebhi if (selector == MLXBF3_GPIO_HW_MODE) {
196d11f9328SAsmaa Mnebhi if (group < MLXBF3_NGPIOS_GPIO0)
197d11f9328SAsmaa Mnebhi writel(BIT(group), priv->fw_ctrl_clr0);
198d11f9328SAsmaa Mnebhi else
199d11f9328SAsmaa Mnebhi writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1);
200d11f9328SAsmaa Mnebhi }
201d11f9328SAsmaa Mnebhi
202d11f9328SAsmaa Mnebhi if (selector == MLXBF3_GPIO_SW_MODE) {
203d11f9328SAsmaa Mnebhi if (group < MLXBF3_NGPIOS_GPIO0)
204d11f9328SAsmaa Mnebhi writel(BIT(group), priv->fw_ctrl_set0);
205d11f9328SAsmaa Mnebhi else
206d11f9328SAsmaa Mnebhi writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1);
207d11f9328SAsmaa Mnebhi }
208d11f9328SAsmaa Mnebhi
209d11f9328SAsmaa Mnebhi return 0;
210d11f9328SAsmaa Mnebhi }
211d11f9328SAsmaa Mnebhi
mlxbf3_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)212d11f9328SAsmaa Mnebhi static int mlxbf3_gpio_request_enable(struct pinctrl_dev *pctldev,
213d11f9328SAsmaa Mnebhi struct pinctrl_gpio_range *range,
214d11f9328SAsmaa Mnebhi unsigned int offset)
215d11f9328SAsmaa Mnebhi {
216d11f9328SAsmaa Mnebhi struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
217d11f9328SAsmaa Mnebhi
218d11f9328SAsmaa Mnebhi if (offset < MLXBF3_NGPIOS_GPIO0)
219d11f9328SAsmaa Mnebhi writel(BIT(offset), priv->fw_ctrl_set0);
220d11f9328SAsmaa Mnebhi else
221d11f9328SAsmaa Mnebhi writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1);
222d11f9328SAsmaa Mnebhi
223d11f9328SAsmaa Mnebhi return 0;
224d11f9328SAsmaa Mnebhi }
225d11f9328SAsmaa Mnebhi
226d11f9328SAsmaa Mnebhi static const struct pinmux_ops mlxbf3_pmx_ops = {
227d11f9328SAsmaa Mnebhi .get_functions_count = mlxbf3_pmx_get_funcs_count,
228d11f9328SAsmaa Mnebhi .get_function_name = mlxbf3_pmx_get_func_name,
229d11f9328SAsmaa Mnebhi .get_function_groups = mlxbf3_pmx_get_groups,
230d11f9328SAsmaa Mnebhi .set_mux = mlxbf3_pmx_set,
231d11f9328SAsmaa Mnebhi .gpio_request_enable = mlxbf3_gpio_request_enable,
232d11f9328SAsmaa Mnebhi };
233d11f9328SAsmaa Mnebhi
234d11f9328SAsmaa Mnebhi static struct pinctrl_desc mlxbf3_pin_desc = {
235d11f9328SAsmaa Mnebhi .name = "pinctrl-mlxbf3",
236d11f9328SAsmaa Mnebhi .pins = mlxbf3_pins,
237d11f9328SAsmaa Mnebhi .npins = ARRAY_SIZE(mlxbf3_pins),
238d11f9328SAsmaa Mnebhi .pctlops = &mlxbf3_pinctrl_group_ops,
239d11f9328SAsmaa Mnebhi .pmxops = &mlxbf3_pmx_ops,
240d11f9328SAsmaa Mnebhi .owner = THIS_MODULE,
241d11f9328SAsmaa Mnebhi };
242d11f9328SAsmaa Mnebhi
243d11f9328SAsmaa Mnebhi static_assert(ARRAY_SIZE(mlxbf3_pinctrl_single_group_names) == MLXBF3_MAX_GPIO_PINS);
244d11f9328SAsmaa Mnebhi
mlxbf3_pinctrl_probe(struct platform_device * pdev)245d11f9328SAsmaa Mnebhi static int mlxbf3_pinctrl_probe(struct platform_device *pdev)
246d11f9328SAsmaa Mnebhi {
247d11f9328SAsmaa Mnebhi struct device *dev = &pdev->dev;
248d11f9328SAsmaa Mnebhi struct mlxbf3_pinctrl *priv;
249d11f9328SAsmaa Mnebhi int ret;
250d11f9328SAsmaa Mnebhi
251d11f9328SAsmaa Mnebhi priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
252d11f9328SAsmaa Mnebhi if (!priv)
253d11f9328SAsmaa Mnebhi return -ENOMEM;
254d11f9328SAsmaa Mnebhi
255d11f9328SAsmaa Mnebhi priv->dev = &pdev->dev;
256d11f9328SAsmaa Mnebhi
257d11f9328SAsmaa Mnebhi priv->fw_ctrl_set0 = devm_platform_ioremap_resource(pdev, 0);
258d11f9328SAsmaa Mnebhi if (IS_ERR(priv->fw_ctrl_set0))
259d11f9328SAsmaa Mnebhi return PTR_ERR(priv->fw_ctrl_set0);
260d11f9328SAsmaa Mnebhi
261d11f9328SAsmaa Mnebhi priv->fw_ctrl_clr0 = devm_platform_ioremap_resource(pdev, 1);
262*0cd9f140SChen Ni if (IS_ERR(priv->fw_ctrl_clr0))
263*0cd9f140SChen Ni return PTR_ERR(priv->fw_ctrl_clr0);
264d11f9328SAsmaa Mnebhi
265d11f9328SAsmaa Mnebhi priv->fw_ctrl_set1 = devm_platform_ioremap_resource(pdev, 2);
266*0cd9f140SChen Ni if (IS_ERR(priv->fw_ctrl_set1))
267*0cd9f140SChen Ni return PTR_ERR(priv->fw_ctrl_set1);
268d11f9328SAsmaa Mnebhi
269d11f9328SAsmaa Mnebhi priv->fw_ctrl_clr1 = devm_platform_ioremap_resource(pdev, 3);
270*0cd9f140SChen Ni if (IS_ERR(priv->fw_ctrl_clr1))
271*0cd9f140SChen Ni return PTR_ERR(priv->fw_ctrl_clr1);
272d11f9328SAsmaa Mnebhi
273d11f9328SAsmaa Mnebhi ret = devm_pinctrl_register_and_init(dev,
274d11f9328SAsmaa Mnebhi &mlxbf3_pin_desc,
275d11f9328SAsmaa Mnebhi priv,
276d11f9328SAsmaa Mnebhi &priv->pctl);
277d11f9328SAsmaa Mnebhi if (ret)
278d11f9328SAsmaa Mnebhi return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
279d11f9328SAsmaa Mnebhi
280d11f9328SAsmaa Mnebhi ret = pinctrl_enable(priv->pctl);
281d11f9328SAsmaa Mnebhi if (ret)
282d11f9328SAsmaa Mnebhi return dev_err_probe(dev, ret, "Failed to enable pinctrl\n");
283d11f9328SAsmaa Mnebhi
284d11f9328SAsmaa Mnebhi pinctrl_add_gpio_ranges(priv->pctl, mlxbf3_pinctrl_gpio_ranges, 2);
285d11f9328SAsmaa Mnebhi
286d11f9328SAsmaa Mnebhi return 0;
287d11f9328SAsmaa Mnebhi }
288d11f9328SAsmaa Mnebhi
289d11f9328SAsmaa Mnebhi static const struct acpi_device_id mlxbf3_pinctrl_acpi_ids[] = {
290d11f9328SAsmaa Mnebhi { "MLNXBF34", 0 },
291d11f9328SAsmaa Mnebhi {}
292d11f9328SAsmaa Mnebhi };
293d11f9328SAsmaa Mnebhi MODULE_DEVICE_TABLE(acpi, mlxbf3_pinctrl_acpi_ids);
294d11f9328SAsmaa Mnebhi
295d11f9328SAsmaa Mnebhi static struct platform_driver mlxbf3_pinctrl_driver = {
296d11f9328SAsmaa Mnebhi .driver = {
297d11f9328SAsmaa Mnebhi .name = "pinctrl-mlxbf3",
298d11f9328SAsmaa Mnebhi .acpi_match_table = mlxbf3_pinctrl_acpi_ids,
299d11f9328SAsmaa Mnebhi },
300d11f9328SAsmaa Mnebhi .probe = mlxbf3_pinctrl_probe,
301d11f9328SAsmaa Mnebhi };
302d11f9328SAsmaa Mnebhi module_platform_driver(mlxbf3_pinctrl_driver);
303d11f9328SAsmaa Mnebhi
304d11f9328SAsmaa Mnebhi MODULE_DESCRIPTION("NVIDIA pinctrl driver");
305d11f9328SAsmaa Mnebhi MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
306d11f9328SAsmaa Mnebhi MODULE_LICENSE("Dual BSD/GPL");
307