| /linux/drivers/gpu/drm/tests/ |
| H A D | drm_dp_mst_helper_test.c | 73 int lane_count; member
94 .lane_count = 4,
99 .lane_count = 2,
104 .lane_count = 1,
109 .lane_count = 4,
114 .lane_count = 2,
119 .lane_count = 1,
124 .lane_count = 4,
129 .lane_count = 2,
134 .lane_count = 1,
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dp_link_training.c | 794 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
797 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
817 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
822 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_get_lane_adjust_vswing_preemph()
891 crtc_state->lane_count, in intel_dp_get_adjust_train()
898 crtc_state->lane_count, in intel_dp_get_adjust_train()
939 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); in intel_dp_set_link_train()
940 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
1010 crtc_state->lane_count, in intel_dp_set_signal_levels()
1017 crtc_state->lane_count, in intel_dp_set_signal_levels()
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| H A D | intel_dp_link_caps.c | 290 if (!link_caps->forced_params.lane_count) in forced_lane_count()
293 return clamp(link_caps->forced_params.lane_count, in forced_lane_count()
315 forced_params->lane_count = forced_lane_count(link_caps); in intel_dp_link_caps_get_forced_params()
336 config->lane_count = intel_dp_link_config_lane_count(lce); in to_intel_dp_link_config()
444 if (forced_params->lane_count && in calc_allowed_config_filter()
445 forced_params->lane_count != config.lane_count) in calc_allowed_config_filter()
451 if (config.lane_count > max_limits->lane_count) in calc_allowed_config_filter()
579 iter_config.lane_count == link_config->lane_count) { in find_config_idx()
633 .lane_count = intel_dp_link_caps_max_common_lane_count(link_caps), in reset_max_link_limits()
718 if (max_link_limits->lane_count > INTEL_DP_MAX_LANE_COUNT || in max_link_limits_valid()
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| H A D | intel_dp_mst.c | 190 crtc_state->lane_count, in intel_dp_mst_bw_overhead()
206 intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, in intel_dp_mst_compute_m_n()
283 crtc_state->lane_count); in intel_dp_mtp_tu_compute_config()
384 remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count); in intel_dp_mtp_tu_compute_config()
408 4 / crtc_state->lane_count); in intel_dp_mtp_tu_compute_config()
461 crtc_state->lane_count = max_link_config.lane_count; in mst_stream_compute_link_config()
498 crtc_state->lane_count = max_link_config.lane_count; in mst_stream_dsc_compute_link_config()
789 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in mst_stream_compute_config()
1217 int link_rate, int lane_count) in intel_mst_probed_link_params_valid() argument
1220 intel_dp->link.mst_probed_lane_count == lane_count; in intel_mst_probed_link_params_valid()
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| H A D | intel_lt_phy.c | 1099 intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count) in intel_lt_phy_setup_powerdown() argument
1118 u8 lane_count) in intel_lt_phy_lane_reset() argument
1142 intel_lt_phy_setup_powerdown(encoder, lane_count); in intel_lt_phy_lane_reset()
1770 hw_state->ltpll.lane_count = crtc_state->lane_count; in intel_lt_phy_pll_calc_state()
1776 hw_state->ltpll.lane_count = crtc_state->lane_count; in intel_lt_phy_pll_calc_state()
1827 u8 lane_count = ltpll->lane_count; in intel_lt_phy_enable_disable_tx() local
1841 switch (lane_count) { in intel_lt_phy_enable_disable_tx()
1865 MISSING_CASE(lane_count); in intel_lt_phy_enable_disable_tx()
1928 intel_lt_phy_lane_reset(encoder, dpll_hw_state->ltpll.lane_count); in intel_lt_phy_pll_enable()
2142 for (ln = 0; ln < crtc_state->lane_count; ln++) { in intel_lt_phy_set_signal_levels()
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| H A D | intel_cx0_phy.c | 515 for (ln = 0; ln < crtc_state->lane_count; ln++) { in intel_cx0_phy_set_signal_levels()
2124 bool is_dp, int port_clock, int lane_count, in intel_c10pll_calc_state_from_table() argument
2140 pll_state->lane_count = lane_count; in intel_c10pll_calc_state_from_table()
2165 crtc_state->port_clock, crtc_state->lane_count, in intel_c10pll_calc_state()
2177 hw_state->cx0pll.lane_count = crtc_state->lane_count; in intel_c10pll_calc_state()
2256 cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0, in intel_c10pll_readout_hw_state()
2662 hw_state->cx0pll.lane_count = crtc_state->lane_count; in intel_c20pll_calc_state()
2712 cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0, in intel_c20pll_readout_hw_state()
2808 hw_state->lane_count, str_yes_no(hw_state->ssc_enabled), in intel_cx0pll_dump_hw_state()
3111 static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count, in intel_cx0_program_phy_lane() argument
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| H A D | intel_dp.c | 384 int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, in intel_dp_link_bw_overhead() argument
398 overhead = drm_dp_bw_overhead(lane_count, hdisplay, in intel_dp_link_bw_overhead()
414 int intel_dp_link_required(int link_clock, int lane_count, in intel_dp_link_required() argument
418 int bw_overhead = intel_dp_link_bw_overhead(link_clock, lane_count, mode_hdisplay, in intel_dp_link_required()
1338 max_lanes = max_bw_config.lane_count; in intel_dp_mode_valid_format()
1736 link_config.lane_count, in intel_dp_compute_link_config_wide()
1742 link_config.lane_count); in intel_dp_compute_link_config_wide()
1745 pipe_config->lane_count = link_config.lane_count; in intel_dp_compute_link_config_wide()
1932 int link_clock, int lane_count, in is_bw_sufficient_for_dsc_config() argument
1940 available_bw = intel_dp_max_link_data_rate(intel_dp, link_clock, lane_count); in is_bw_sufficient_for_dsc_config()
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| H A D | intel_ddi.c | 361 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | in intel_ddi_init_dp_buf_reg()
589 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
599 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
612 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
1165 if (crtc_state->lane_count == 4) in icl_combo_phy_loadgen_select()
2215 width = crtc_state->lane_count; in icl_program_mg_dp_mode()
2489 crtc_state->lane_count, in intel_ddi_power_up_lanes()
2609 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); in mtl_port_buf_ctl_program()
2648 crtc_state->lane_count); in mtl_ddi_pre_enable_dp()
2764 crtc_state->lane_count); in tgl_ddi_pre_enable_dp()
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| H A D | intel_display_types.h | 1218 u8 lane_count; member
1817 int lane_count; member
1827 u8 lane_count; member
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| H A D | intel_psr.c | 1315 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
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| /linux/drivers/gpu/drm/msm/dp/ |
| H A D | dp_panel.h | 84 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
86 return (lane_count == 1 || in is_lane_count_valid()
87 lane_count == 2 || in is_lane_count_valid()
88 lane_count == 4); in is_lane_count_valid()
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| H A D | dp_audio.h | 21 u32 lane_count; member
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| H A D | dp_ctrl.c | 177 u8 lane_count, bw_code; in msm_dp_aux_link_configure() local
180 lane_count = link->num_lanes; in msm_dp_aux_link_configure()
183 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; in msm_dp_aux_link_configure()
185 err = drm_dp_dpcd_writeb(aux, DP_LANE_COUNT_SET, lane_count); in msm_dp_aux_link_configure()
2304 int lane_count) in msm_dp_ctrl_clock_recovery_any_ok() argument
2308 if (lane_count <= 1) in msm_dp_ctrl_clock_recovery_any_ok()
2316 reduced_cnt = lane_count >> 1; in msm_dp_ctrl_clock_recovery_any_ok()
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| H A D | dp_audio.c | 208 switch (audio->msm_dp_audio.lane_count) { in msm_dp_audio_safe_to_exit_level()
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| H A D | dp_display.c | 685 dp->audio->lane_count = dp->link->link_params.num_lanes; in msm_dp_display_post_enable()
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| /linux/include/drm/display/ |
| H A D | drm_dp_helper.h | 37 int lane_count);
39 int lane_count);
63 int lane_count);
65 int lane_count);
1025 int drm_dp_bw_overhead(int lane_count, int hactive,
1032 int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
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| /linux/drivers/gpu/drm/display/ |
| H A D | drm_dp_helper.c | 93 int lane_count) in drm_dp_channel_eq_ok() argument
103 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
113 int lane_count) in drm_dp_clock_recovery_ok() argument
118 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
177 int lane_count) in drm_dp_128b132b_lane_channel_eq_done() argument
186 for (lane = 0; lane < lane_count; lane++) { in drm_dp_128b132b_lane_channel_eq_done()
197 int lane_count) in drm_dp_128b132b_lane_symbol_locked() argument
202 for (lane = 0; lane < lane_count; lane++) { in drm_dp_128b132b_lane_symbol_locked()
4734 static int drm_dp_link_data_symbol_cycles(int lane_count, int pixels, in drm_dp_link_data_symbol_cycles()
4738 int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count); in drm_dp_link_data_symbol_cycles()
4732 drm_dp_link_data_symbol_cycles(int lane_count,int pixels,int bpp_x16,int symbol_size,bool is_mst) drm_dp_link_data_symbol_cycles() argument
4754 drm_dp_link_symbol_cycles(int lane_count,int pixels,int dsc_slice_count,int bpp_x16,int symbol_size,bool is_mst) drm_dp_link_symbol_cycles() argument
4798 drm_dp_bw_overhead(int lane_count,int hactive,int dsc_slice_count,int bpp_x16,unsigned long flags) drm_dp_bw_overhead() argument
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training_fixed_vs_pe_retimer.h | 39 uint8_t lane_count);
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| H A D | link_dp_dpia_bw.c | 244 link->reported_link_cap.lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count; in link_dpia_enable_usb4_dp_bw_alloc_mode()
354 (uint32_t)link_cap->lane_count * in link_dpia_get_dp_overhead()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_debugfs.c | 212 link->cur_link_settings.lane_count, in dp_link_settings_read()
218 link->verified_link_cap.lane_count, in dp_link_settings_read()
224 link->reported_link_cap.lane_count, in dp_link_settings_read()
230 link->preferred_link_setting.lane_count, in dp_link_settings_read()
333 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write()
467 prefer_link_settings.lane_count = param[0]; in dp_mst_link_setting()
662 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
663 link->preferred_link_setting.lane_count; in dp_phy_settings_write()
669 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
670 link->cur_link_settings.lane_count; in dp_phy_settings_write()
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| H A D | amdgpu_dm_helpers.c | 653 link->cur_link_settings.lane_count = 0; in dm_helpers_dp_mst_stop_top_mgr()
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| H A D | amdgpu_dm_connector.c | 2166 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; in dm_validate_stream_and_context()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_detection.c | 579 link->cur_link_settings.lane_count = in read_current_link_settings_on_detect()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/tests/ |
| H A D | amdgpu_dm_helpers_test.c | 3224 link->cur_link_settings.lane_count = 4; in dm_test_mst_stop_top_mgr_active()
3228 KUNIT_EXPECT_EQ(test, link->cur_link_settings.lane_count, 0); in dm_test_mst_stop_top_mgr_active()
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| H A D | amdgpu_dm_connector_test.c | 4670 KUNIT_EXPECT_EQ(test, (int)ctx->link->verified_link_cap.lane_count, in dm_test_native_mode_empty_probed_zeroes_clock()
4692 KUNIT_EXPECT_EQ(test, (int)ctx->link->verified_link_cap.lane_count, 0); in dm_test_native_mode_copies_preferred()
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