1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services_types.h" 28 #include "dc.h" 29 #include "dc/dc_dmub_srv.h" 30 #include "dc/dc_edid_parser.h" 31 #include "dc/dc_stat.h" 32 #include "dc/dc_state.h" 33 #include "dc/dc_stream.h" 34 #include "dc/inc/core_types.h" 35 #include "link_enc_cfg.h" 36 #include "link/protocols/link_dpcd.h" 37 #include "link_service_types.h" 38 #include "link/protocols/link_dp_capability.h" 39 #include "link/protocols/link_ddc.h" 40 41 #include "amdgpu.h" 42 #include "amdgpu_display.h" 43 #include "amdgpu_dm.h" 44 #include "amdgpu_dm_connector.h" 45 #include "amdgpu_dm_plane.h" 46 #include "amdgpu_dm_crtc.h" 47 #include "amdgpu_dm_wb.h" 48 #include "amdgpu_dm_mst_types.h" 49 #if defined(CONFIG_DEBUG_FS) 50 #include "amdgpu_dm_debugfs.h" 51 #endif 52 #include "amdgpu_dm_backlight.h" 53 #include "amdgpu_dm_audio.h" 54 #include "amdgpu_dm_irq.h" 55 #include "amdgpu_dm_psr.h" 56 #include "dm_helpers.h" 57 58 #include <drm/drm_atomic.h> 59 #include <drm/drm_atomic_uapi.h> 60 #include <drm/drm_atomic_helper.h> 61 #include <drm/drm_edid.h> 62 #include <drm/drm_eld.h> 63 #include <drm/drm_fixed.h> 64 #include <drm/drm_mode.h> 65 #include <drm/drm_probe_helper.h> 66 #include <drm/drm_utils.h> 67 #include <drm/display/drm_dp_mst_helper.h> 68 #include <drm/display/drm_hdmi_helper.h> 69 #include <drm/drm_privacy_screen_consumer.h> 70 #include <drm/display/drm_hdcp_helper.h> 71 72 #include <linux/backlight.h> 73 74 #include <media/cec-notifier.h> 75 76 #include "modules/inc/mod_freesync.h" 77 #include "modules/inc/mod_power.h" 78 79 #include "amdgpu_dm_trace.h" 80 81 /* Encoder functions */ 82 83 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 84 { 85 drm_encoder_cleanup(encoder); 86 kfree(encoder); 87 } 88 89 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 90 .destroy = amdgpu_dm_encoder_destroy, 91 }; 92 93 STATIC_IFN_KUNIT void dm_encoder_helper_disable(struct drm_encoder *encoder) 94 { 95 } 96 EXPORT_IF_KUNIT(dm_encoder_helper_disable); 97 98 STATIC_IFN_KUNIT int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 99 struct drm_crtc_state *crtc_state, 100 struct drm_connector_state *conn_state) 101 { 102 struct drm_atomic_commit *state = crtc_state->state; 103 struct drm_connector *connector = conn_state->connector; 104 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 105 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 106 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 107 struct drm_dp_mst_topology_mgr *mst_mgr; 108 struct drm_dp_mst_port *mst_port; 109 struct drm_dp_mst_topology_state *mst_state; 110 enum dc_color_depth color_depth; 111 int clock, bpp = 0; 112 bool is_y420 = false; 113 114 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 115 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 116 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 117 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 118 enum drm_mode_status result; 119 120 result = drm_crtc_helper_mode_valid_fixed(encoder->crtc, adjusted_mode, native_mode); 121 if (result != MODE_OK && dm_new_connector_state->scaling == RMX_OFF) { 122 drm_dbg_driver(encoder->dev, 123 "mode %dx%d@%dHz is not native, enabling scaling\n", 124 adjusted_mode->hdisplay, adjusted_mode->vdisplay, 125 drm_mode_vrefresh(adjusted_mode)); 126 dm_new_connector_state->scaling = RMX_ASPECT; 127 } 128 return 0; 129 } 130 131 if (!aconnector->mst_output_port) 132 return 0; 133 134 mst_port = aconnector->mst_output_port; 135 mst_mgr = &aconnector->mst_root->mst_mgr; 136 137 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 138 return 0; 139 140 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 141 if (IS_ERR(mst_state)) 142 return PTR_ERR(mst_state); 143 144 mst_state->pbn_div.full = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); 145 146 if (!state->duplicated) { 147 int max_bpc = conn_state->max_requested_bpc; 148 149 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 150 aconnector->force_yuv_pixel_format == PIXEL_ENCODING_YCBCR420; 151 color_depth = amdgpu_dm_convert_color_depth_from_display_info(connector, 152 is_y420, 153 max_bpc); 154 bpp = amdgpu_dm_convert_dc_color_depth_into_bpc(color_depth) * 3; 155 clock = adjusted_mode->clock; 156 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); 157 } 158 159 dm_new_connector_state->vcpi_slots = 160 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 161 dm_new_connector_state->pbn); 162 if (dm_new_connector_state->vcpi_slots < 0) { 163 drm_dbg_atomic(connector->dev, "failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 164 return dm_new_connector_state->vcpi_slots; 165 } 166 return 0; 167 } 168 EXPORT_IF_KUNIT(dm_encoder_helper_atomic_check); 169 170 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 171 .disable = dm_encoder_helper_disable, 172 .atomic_check = dm_encoder_helper_atomic_check 173 }; 174 175 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 176 { 177 switch (adev->mode_info.num_crtc) { 178 case 1: 179 return 0x1; 180 case 2: 181 return 0x3; 182 case 3: 183 return 0x7; 184 case 4: 185 return 0xf; 186 case 5: 187 return 0x1f; 188 case 6: 189 default: 190 return 0x3f; 191 } 192 } 193 EXPORT_IF_KUNIT(amdgpu_dm_get_encoder_crtc_mask); 194 195 int amdgpu_dm_encoder_init(struct drm_device *dev, 196 struct amdgpu_encoder *aencoder, 197 uint32_t link_index) 198 { 199 struct amdgpu_device *adev = drm_to_adev(dev); 200 201 int res = drm_encoder_init(dev, 202 &aencoder->base, 203 &amdgpu_dm_encoder_funcs, 204 DRM_MODE_ENCODER_TMDS, 205 NULL); 206 207 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 208 209 if (!res) 210 aencoder->encoder_id = link_index; 211 else 212 aencoder->encoder_id = -1; 213 214 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 215 216 return res; 217 } 218 219 STATIC_IFN_KUNIT enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 220 { 221 switch (link->dpcd_caps.dongle_type) { 222 case DISPLAY_DONGLE_NONE: 223 return DRM_MODE_SUBCONNECTOR_Native; 224 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 225 return DRM_MODE_SUBCONNECTOR_VGA; 226 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 227 case DISPLAY_DONGLE_DP_DVI_DONGLE: 228 return DRM_MODE_SUBCONNECTOR_DVID; 229 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 230 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 231 return DRM_MODE_SUBCONNECTOR_HDMIA; 232 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 233 default: 234 return DRM_MODE_SUBCONNECTOR_Unknown; 235 } 236 } 237 EXPORT_IF_KUNIT(get_subconnector_type); 238 239 STATIC_IFN_KUNIT void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 240 { 241 struct dc_link *link = aconnector->dc_link; 242 struct drm_connector *connector = &aconnector->base; 243 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 244 245 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 246 return; 247 248 if (aconnector->dc_sink) 249 subconnector = get_subconnector_type(link); 250 251 drm_object_property_set_value(&connector->base, 252 connector->dev->mode_config.dp_subconnector_property, 253 subconnector); 254 } 255 EXPORT_IF_KUNIT(update_subconnector_property); 256 257 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 258 259 STATIC_IFN_KUNIT void amdgpu_dm_fbc_init(struct drm_connector *connector) 260 { 261 struct amdgpu_device *adev = drm_to_adev(connector->dev); 262 struct dm_compressor_info *compressor = &adev->dm.compressor; 263 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 264 struct drm_display_mode *mode; 265 unsigned long max_size = 0; 266 267 if (adev->dm.dc->fbc_compressor == NULL) 268 return; 269 270 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 271 return; 272 273 if (compressor->bo_ptr) 274 return; 275 276 277 list_for_each_entry(mode, &connector->modes, head) { 278 if (max_size < (unsigned long) mode->htotal * mode->vtotal) 279 max_size = (unsigned long) mode->htotal * mode->vtotal; 280 } 281 282 if (max_size) { 283 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 284 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 285 &compressor->gpu_addr, &compressor->cpu_addr); 286 287 if (r) 288 drm_err(adev_to_drm(adev), "DM: Failed to initialize FBC\n"); 289 else { 290 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 291 drm_info(adev_to_drm(adev), "DM: FBC alloc %lu\n", max_size*4); 292 } 293 294 } 295 296 } 297 EXPORT_IF_KUNIT(amdgpu_dm_fbc_init); 298 299 300 int amdgpu_dm_detect_mst_link_for_all_connectors(struct drm_device *dev) 301 { 302 struct amdgpu_dm_connector *aconnector; 303 struct drm_connector *connector; 304 struct drm_connector_list_iter iter; 305 int ret = 0; 306 307 drm_connector_list_iter_begin(dev, &iter); 308 drm_for_each_connector_iter(connector, &iter) { 309 310 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 311 continue; 312 313 aconnector = to_amdgpu_dm_connector(connector); 314 if (aconnector->dc_link->type == dc_connection_mst_branch && 315 aconnector->mst_mgr.aux) { 316 drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p [id: %d]\n", 317 aconnector, 318 aconnector->base.base.id); 319 320 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 321 if (ret < 0) { 322 drm_err(dev, "DM_MST: Failed to start MST\n"); 323 aconnector->dc_link->type = 324 dc_connection_single; 325 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 326 aconnector->dc_link); 327 break; 328 } 329 } 330 } 331 drm_connector_list_iter_end(&iter); 332 333 return ret; 334 } 335 EXPORT_IF_KUNIT(amdgpu_dm_detect_mst_link_for_all_connectors); 336 337 STATIC_IFN_KUNIT void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector) 338 { 339 struct cec_notifier *n = aconnector->notifier; 340 341 if (!n) 342 return; 343 344 cec_notifier_phys_addr_invalidate(n); 345 } 346 EXPORT_IF_KUNIT(hdmi_cec_unset_edid); 347 348 void amdgpu_dm_hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector) 349 { 350 struct drm_connector *connector = &aconnector->base; 351 struct cec_notifier *n = aconnector->notifier; 352 353 if (!n) 354 return; 355 356 cec_notifier_set_phys_addr(n, 357 connector->display_info.source_physical_address); 358 } 359 EXPORT_IF_KUNIT(amdgpu_dm_hdmi_cec_set_edid); 360 361 void amdgpu_dm_s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend) 362 { 363 struct amdgpu_dm_connector *aconnector; 364 struct drm_connector *connector; 365 struct drm_connector_list_iter conn_iter; 366 367 drm_connector_list_iter_begin(ddev, &conn_iter); 368 drm_for_each_connector_iter(connector, &conn_iter) { 369 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 370 continue; 371 372 aconnector = to_amdgpu_dm_connector(connector); 373 if (suspend) 374 hdmi_cec_unset_edid(aconnector); 375 else 376 amdgpu_dm_hdmi_cec_set_edid(aconnector); 377 } 378 drm_connector_list_iter_end(&conn_iter); 379 } 380 EXPORT_IF_KUNIT(amdgpu_dm_s3_handle_hdmi_cec); 381 382 383 struct drm_connector * 384 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_commit *state, 385 struct drm_crtc *crtc) 386 { 387 u32 i; 388 struct drm_connector_state *new_con_state; 389 struct drm_connector *connector; 390 struct drm_crtc *crtc_from_state; 391 392 for_each_new_connector_in_state(state, connector, new_con_state, i) { 393 crtc_from_state = new_con_state->crtc; 394 395 if (crtc_from_state == crtc) 396 return connector; 397 } 398 399 return NULL; 400 } 401 EXPORT_IF_KUNIT(amdgpu_dm_find_first_crtc_matching_connector); 402 403 STATIC_IFN_KUNIT void amdgpu_dm_set_panel_type(struct amdgpu_dm_connector *aconnector) 404 { 405 struct drm_connector *connector = &aconnector->base; 406 struct drm_display_info *display_info = &connector->display_info; 407 struct dc_link *link = aconnector->dc_link; 408 struct amdgpu_device *adev; 409 enum dc_panel_type panel_type = PANEL_TYPE_NONE; 410 411 adev = drm_to_adev(connector->dev); 412 413 switch (display_info->amd_vsdb.panel_type) { 414 case AMD_VSDB_PANEL_TYPE_OLED: 415 panel_type = PANEL_TYPE_OLED; 416 break; 417 case AMD_VSDB_PANEL_TYPE_MINILED: 418 panel_type = PANEL_TYPE_MINILED; 419 break; 420 } 421 422 /* If VSDB didn't determine panel type, check DPCD ext caps */ 423 if (panel_type == PANEL_TYPE_NONE) { 424 if (link->dpcd_sink_ext_caps.bits.miniled == 1) 425 panel_type = PANEL_TYPE_MINILED; 426 if (link->dpcd_sink_ext_caps.bits.oled == 1) 427 panel_type = PANEL_TYPE_OLED; 428 } 429 430 /* If VSDB and DPCD didn't determine panel type, check DID */ 431 if (panel_type == PANEL_TYPE_NONE) { 432 if (display_info->panel_type == DRM_MODE_PANEL_TYPE_LCD) 433 panel_type = PANEL_TYPE_LCD; 434 else if (display_info->panel_type == DRM_MODE_PANEL_TYPE_OLED) 435 panel_type = PANEL_TYPE_OLED; 436 } 437 438 if (panel_type == PANEL_TYPE_NONE) { 439 struct drm_amd_vsdb_info *vsdb = &display_info->amd_vsdb; 440 u32 lum1_max = vsdb->luminance_range1.max_luminance; 441 u32 lum2_max = vsdb->luminance_range2.max_luminance; 442 443 if (vsdb->version && link->local_sink && 444 link->local_sink->edid_caps.manufacturer_id == 445 DDC_MANUFACTURERNAME_SAMSUNG && 446 lum1_max >= ((lum2_max * 3) / 2)) 447 panel_type = PANEL_TYPE_MINILED; 448 } 449 450 if (panel_type != PANEL_TYPE_NONE) 451 link->panel_type = panel_type; 452 else 453 link->panel_type = PANEL_TYPE_LCD; 454 455 if (link->panel_type == PANEL_TYPE_OLED) 456 drm_object_property_set_value(&connector->base, 457 adev_to_drm(adev)->mode_config.panel_type_property, 458 DRM_MODE_PANEL_TYPE_OLED); 459 else if (link->panel_type == PANEL_TYPE_LCD) 460 drm_object_property_set_value(&connector->base, 461 adev_to_drm(adev)->mode_config.panel_type_property, 462 DRM_MODE_PANEL_TYPE_LCD); 463 else 464 drm_object_property_set_value(&connector->base, 465 adev_to_drm(adev)->mode_config.panel_type_property, 466 DRM_MODE_PANEL_TYPE_UNKNOWN); 467 468 drm_dbg_kms(aconnector->base.dev, "Panel type: %d\n", link->panel_type); 469 } 470 EXPORT_IF_KUNIT(amdgpu_dm_set_panel_type); 471 472 STATIC_IFN_KUNIT void amdgpu_dm_update_cacp_caps(struct amdgpu_dm_connector *aconnector) 473 { 474 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 475 struct dc_link *link = aconnector->dc_link; 476 477 link->panel_config.cacp.cacp_supported = true; 478 479 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 1, 4) || 480 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 1, 6)) { 481 link->panel_config.cacp.cacp_supported = false; 482 return; 483 } 484 485 if (link->connector_signal != SIGNAL_TYPE_EDP && 486 link->connector_signal != SIGNAL_TYPE_LVDS) { 487 link->panel_config.cacp.cacp_supported = false; 488 return; 489 } 490 491 if (link->panel_type == PANEL_TYPE_LCD) 492 link->panel_config.cacp.cacp_supported = false; 493 494 drm_dbg_kms(aconnector->base.dev, "cacp_supported: %d\n", 495 link->panel_config.cacp.cacp_supported); 496 } 497 EXPORT_IF_KUNIT(amdgpu_dm_update_cacp_caps); 498 499 DEFINE_FREE(sink_release, struct dc_sink *, if (_T) dc_sink_release(_T)) 500 501 void amdgpu_dm_update_connector_after_detect( 502 struct amdgpu_dm_connector *aconnector) 503 { 504 struct drm_connector *connector = &aconnector->base; 505 struct dc_sink *sink __free(sink_release) = NULL; 506 struct drm_device *dev = connector->dev; 507 struct amdgpu_device *adev = drm_to_adev(dev); 508 int inst; 509 510 /* MST handled by drm_mst framework */ 511 if (aconnector->mst_mgr.mst_state) 512 return; 513 514 sink = aconnector->dc_link->local_sink; 515 if (sink) 516 dc_sink_retain(sink); 517 518 /* 519 * Edid mgmt connector gets first update only in mode_valid hook and then 520 * the connector sink is set to either fake or physical sink depends on link status. 521 * Skip if already done during boot. 522 */ 523 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 524 && aconnector->dc_em_sink) { 525 526 /* 527 * For S3 resume with headless use eml_sink to fake stream 528 * because on resume connector->sink is set to NULL 529 */ 530 guard(mutex)(&dev->mode_config.mutex); 531 532 if (sink) { 533 if (aconnector->dc_sink) { 534 amdgpu_dm_update_freesync_caps(connector, NULL, true); 535 /* 536 * retain and release below are used to 537 * bump up refcount for sink because the link doesn't point 538 * to it anymore after disconnect, so on next crtc to connector 539 * reshuffle by UMD we will get into unwanted dc_sink release 540 */ 541 dc_sink_release(aconnector->dc_sink); 542 } 543 aconnector->dc_sink = sink; 544 dc_sink_retain(aconnector->dc_sink); 545 amdgpu_dm_update_freesync_caps(connector, 546 aconnector->drm_edid, true); 547 } else { 548 amdgpu_dm_update_freesync_caps(connector, NULL, true); 549 if (!aconnector->dc_sink) { 550 aconnector->dc_sink = aconnector->dc_em_sink; 551 dc_sink_retain(aconnector->dc_sink); 552 } 553 } 554 555 return; 556 } 557 558 /* 559 * TODO: temporary guard to look for proper fix 560 * if this sink is MST sink, we should not do anything 561 */ 562 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 563 return; 564 565 if (aconnector->dc_sink == sink) { 566 /* 567 * We got a DP short pulse (Link Loss, DP CTS, etc...). 568 * Do nothing!! 569 */ 570 drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't change.\n", 571 aconnector->connector_id); 572 return; 573 } 574 575 drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 576 aconnector->connector_id, aconnector->dc_sink, sink); 577 578 /* When polling, DRM has already locked the mutex for us. */ 579 if (!drm_kms_helper_is_poll_worker()) 580 mutex_lock(&dev->mode_config.mutex); 581 582 /* 583 * 1. Update status of the drm connector 584 * 2. Send an event and let userspace tell us what to do 585 */ 586 if (sink) { 587 /* 588 * TODO: check if we still need the S3 mode update workaround. 589 * If yes, put it here. 590 */ 591 if (aconnector->dc_sink) { 592 amdgpu_dm_update_freesync_caps(connector, NULL, true); 593 dc_sink_release(aconnector->dc_sink); 594 } 595 596 aconnector->dc_sink = sink; 597 dc_sink_retain(aconnector->dc_sink); 598 drm_edid_free(aconnector->drm_edid); 599 aconnector->drm_edid = NULL; 600 if (sink->dc_edid.length == 0) { 601 hdmi_cec_unset_edid(aconnector); 602 if (aconnector->dc_link->aux_mode) 603 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 604 } else { 605 const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; 606 607 aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); 608 drm_edid_connector_update(connector, aconnector->drm_edid); 609 610 amdgpu_dm_hdmi_cec_set_edid(aconnector); 611 if (aconnector->dc_link->aux_mode) 612 drm_dp_cec_attach(&aconnector->dm_dp_aux.aux, 613 connector->display_info.source_physical_address); 614 } 615 616 if (!aconnector->timing_requested) { 617 aconnector->timing_requested = 618 kzalloc_obj(struct dc_crtc_timing); 619 if (!aconnector->timing_requested) 620 drm_err(dev, 621 "failed to create aconnector->requested_timing\n"); 622 } 623 624 amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid, true); 625 amdgpu_dm_update_connector_ext_caps(aconnector); 626 amdgpu_dm_set_panel_type(aconnector); 627 amdgpu_dm_update_cacp_caps(aconnector); 628 629 if (aconnector->hdmi_comp_auto) { 630 if (sink->sink_signal != SIGNAL_TYPE_HDMI_FRL) 631 sink->sink_signal = SIGNAL_TYPE_HDMI_FRL; 632 } 633 } else { 634 hdmi_cec_unset_edid(aconnector); 635 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 636 amdgpu_dm_update_freesync_caps(connector, NULL, true); 637 aconnector->num_modes = 0; 638 dc_sink_release(aconnector->dc_sink); 639 aconnector->dc_sink = NULL; 640 drm_edid_free(aconnector->drm_edid); 641 aconnector->drm_edid = NULL; 642 kfree(aconnector->timing_requested); 643 aconnector->timing_requested = NULL; 644 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 645 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 646 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 647 648 mutex_lock(&adev->dm.audio_lock); 649 inst = aconnector->audio_inst; 650 aconnector->audio_inst = -1; 651 mutex_unlock(&adev->dm.audio_lock); 652 if (inst != -1) 653 amdgpu_dm_audio_eld_notify(adev, inst); 654 } 655 656 update_subconnector_property(aconnector); 657 658 /* When polling, the mutex will be unlocked for us by DRM. */ 659 if (!drm_kms_helper_is_poll_worker()) 660 mutex_unlock(&dev->mode_config.mutex); 661 } 662 EXPORT_IF_KUNIT(amdgpu_dm_update_connector_after_detect); 663 664 enum dc_color_depth 665 amdgpu_dm_convert_color_depth_from_display_info(const struct drm_connector *connector, 666 bool is_y420, int requested_bpc) 667 { 668 u8 bpc; 669 670 if (is_y420) { 671 bpc = 8; 672 673 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 674 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 675 bpc = 16; 676 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 677 bpc = 12; 678 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 679 bpc = 10; 680 } else { 681 bpc = (uint8_t)connector->display_info.bpc; 682 /* Assume 8 bpc by default if no bpc is specified. */ 683 bpc = bpc ? bpc : 8; 684 } 685 686 if (requested_bpc > 0) { 687 /* 688 * Cap display bpc based on the user requested value. 689 * 690 * The value for state->max_bpc may not correctly updated 691 * depending on when the connector gets added to the state 692 * or if this was called outside of atomic check, so it 693 * can't be used directly. 694 */ 695 bpc = min_t(u8, bpc, requested_bpc); 696 697 /* Round down to the nearest even number. */ 698 bpc = bpc - (bpc & 1); 699 } 700 701 switch (bpc) { 702 case 0: 703 /* 704 * Temporary Work around, DRM doesn't parse color depth for 705 * EDID revision before 1.4 706 * TODO: Fix edid parsing 707 */ 708 return COLOR_DEPTH_888; 709 case 6: 710 return COLOR_DEPTH_666; 711 case 8: 712 return COLOR_DEPTH_888; 713 case 10: 714 return COLOR_DEPTH_101010; 715 case 12: 716 return COLOR_DEPTH_121212; 717 case 14: 718 return COLOR_DEPTH_141414; 719 case 16: 720 return COLOR_DEPTH_161616; 721 default: 722 return COLOR_DEPTH_UNDEFINED; 723 } 724 } 725 EXPORT_IF_KUNIT(amdgpu_dm_convert_color_depth_from_display_info); 726 727 STATIC_IFN_KUNIT enum dc_aspect_ratio 728 get_aspect_ratio(const struct drm_display_mode *mode_in) 729 { 730 /* 1-1 mapping, since both enums follow the HDMI spec. */ 731 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 732 } 733 EXPORT_IF_KUNIT(get_aspect_ratio); 734 735 enum dc_color_space 736 amdgpu_dm_get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 737 const struct drm_connector_state *connector_state) 738 { 739 enum dc_color_space color_space = COLOR_SPACE_SRGB; 740 741 switch (connector_state->colorspace) { 742 case DRM_MODE_COLORIMETRY_BT601_YCC: 743 if (dc_crtc_timing->flags.Y_ONLY) 744 color_space = COLOR_SPACE_YCBCR601_LIMITED; 745 else 746 color_space = COLOR_SPACE_YCBCR601; 747 break; 748 case DRM_MODE_COLORIMETRY_BT709_YCC: 749 if (dc_crtc_timing->flags.Y_ONLY) 750 color_space = COLOR_SPACE_YCBCR709_LIMITED; 751 else 752 color_space = COLOR_SPACE_YCBCR709; 753 break; 754 case DRM_MODE_COLORIMETRY_OPRGB: 755 color_space = COLOR_SPACE_ADOBERGB; 756 break; 757 case DRM_MODE_COLORIMETRY_BT2020_RGB: 758 case DRM_MODE_COLORIMETRY_BT2020_YCC: 759 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) 760 color_space = COLOR_SPACE_2020_RGB_FULLRANGE; 761 else 762 color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 763 break; 764 case DRM_MODE_COLORIMETRY_DEFAULT: /* ITU601 */ 765 default: 766 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 767 color_space = COLOR_SPACE_SRGB; 768 if (connector_state->hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_LIMITED) 769 color_space = COLOR_SPACE_SRGB_LIMITED; 770 /* 771 * 27030khz is the separation point between HDTV and SDTV 772 * according to HDMI spec, we use YCbCr709 and YCbCr601 773 * respectively 774 */ 775 } else if (dc_crtc_timing->pix_clk_100hz > 270300) { 776 if (dc_crtc_timing->flags.Y_ONLY) 777 color_space = 778 COLOR_SPACE_YCBCR709_LIMITED; 779 else 780 color_space = COLOR_SPACE_YCBCR709; 781 } else { 782 if (dc_crtc_timing->flags.Y_ONLY) 783 color_space = 784 COLOR_SPACE_YCBCR601_LIMITED; 785 else 786 color_space = COLOR_SPACE_YCBCR601; 787 } 788 break; 789 } 790 791 return color_space; 792 } 793 EXPORT_IF_KUNIT(amdgpu_dm_get_output_color_space); 794 795 STATIC_IFN_KUNIT enum display_content_type 796 get_output_content_type(const struct drm_connector_state *connector_state) 797 { 798 switch (connector_state->content_type) { 799 default: 800 case DRM_MODE_CONTENT_TYPE_NO_DATA: 801 return DISPLAY_CONTENT_TYPE_NO_DATA; 802 case DRM_MODE_CONTENT_TYPE_GRAPHICS: 803 return DISPLAY_CONTENT_TYPE_GRAPHICS; 804 case DRM_MODE_CONTENT_TYPE_PHOTO: 805 return DISPLAY_CONTENT_TYPE_PHOTO; 806 case DRM_MODE_CONTENT_TYPE_CINEMA: 807 return DISPLAY_CONTENT_TYPE_CINEMA; 808 case DRM_MODE_CONTENT_TYPE_GAME: 809 return DISPLAY_CONTENT_TYPE_GAME; 810 } 811 } 812 EXPORT_IF_KUNIT(get_output_content_type); 813 814 STATIC_IFN_KUNIT bool adjust_colour_depth_from_display_info( 815 struct dc_crtc_timing *timing_out, 816 const struct drm_display_info *info) 817 { 818 enum dc_color_depth depth = timing_out->display_color_depth; 819 int normalized_clk; 820 821 do { 822 normalized_clk = timing_out->pix_clk_100hz / 10; 823 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 824 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 825 normalized_clk /= 2; 826 /* Adjusting pix clock following on HDMI spec based on colour depth */ 827 switch (depth) { 828 case COLOR_DEPTH_888: 829 break; 830 case COLOR_DEPTH_101010: 831 normalized_clk = (normalized_clk * 30) / 24; 832 break; 833 case COLOR_DEPTH_121212: 834 normalized_clk = (normalized_clk * 36) / 24; 835 break; 836 case COLOR_DEPTH_161616: 837 normalized_clk = (normalized_clk * 48) / 24; 838 break; 839 default: 840 /* The above depths are the only ones valid for HDMI. */ 841 return false; 842 } 843 if (normalized_clk <= info->max_tmds_clock) { 844 timing_out->display_color_depth = depth; 845 return true; 846 } 847 } while (--depth > COLOR_DEPTH_666); 848 return false; 849 } 850 EXPORT_IF_KUNIT(adjust_colour_depth_from_display_info); 851 852 STATIC_IFN_KUNIT void fill_stream_properties_from_drm_display_mode( 853 struct dc_stream_state *stream, 854 const struct drm_display_mode *mode_in, 855 const struct drm_connector *connector, 856 const struct drm_connector_state *connector_state, 857 const struct dc_stream_state *old_stream, 858 int requested_bpc, 859 enum dc_pixel_encoding requested_encoding, 860 bool is_hdmi_ep) 861 { 862 struct dc_crtc_timing *timing_out = &stream->timing; 863 const struct drm_display_info *info = &connector->display_info; 864 struct amdgpu_dm_connector *aconnector = NULL; 865 struct hdmi_vendor_infoframe hv_frame; 866 struct hdmi_avi_infoframe avi_frame; 867 ssize_t err; 868 869 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 870 aconnector = to_amdgpu_dm_connector(connector); 871 872 memset(&hv_frame, 0, sizeof(hv_frame)); 873 memset(&avi_frame, 0, sizeof(avi_frame)); 874 875 timing_out->h_border_left = 0; 876 timing_out->h_border_right = 0; 877 timing_out->v_border_top = 0; 878 timing_out->v_border_bottom = 0; 879 880 /* 881 * The pixel encoding to use is decided entirely by the caller (see 882 * amdgpu_dm_create_validate_stream_for_sink()), which enumerates only 883 * the encodings the sink actually advertises. This helper must not 884 * second-guess that choice; it simply applies it. 885 */ 886 timing_out->pixel_encoding = requested_encoding; 887 888 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 889 timing_out->display_color_depth = amdgpu_dm_convert_color_depth_from_display_info( 890 connector, 891 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 892 requested_bpc); 893 timing_out->scan_type = SCANNING_TYPE_NODATA; 894 timing_out->hdmi_vic = 0; 895 896 if (old_stream) { 897 timing_out->vic = old_stream->timing.vic; 898 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 899 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 900 } else { 901 timing_out->vic = drm_match_cea_mode(mode_in); 902 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 903 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 904 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 905 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 906 } 907 908 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 909 stream->signal == SIGNAL_TYPE_HDMI_FRL) { 910 err = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, 911 (struct drm_connector *)connector, 912 mode_in); 913 if (err < 0) 914 drm_warn_once(connector->dev, "Failed to setup avi infoframe on connector %s: %zd\n", 915 connector->name, err); 916 timing_out->vic = avi_frame.video_code; 917 err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, 918 (struct drm_connector *)connector, 919 mode_in); 920 if (err < 0) 921 drm_warn_once(connector->dev, "Failed to setup vendor infoframe on connector %s: %zd\n", 922 connector->name, err); 923 timing_out->hdmi_vic = hv_frame.vic; 924 } 925 926 if (aconnector && amdgpu_dm_is_freesync_video_mode(mode_in, aconnector)) { 927 timing_out->h_addressable = mode_in->hdisplay; 928 timing_out->h_total = mode_in->htotal; 929 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 930 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 931 timing_out->v_total = mode_in->vtotal; 932 timing_out->v_addressable = mode_in->vdisplay; 933 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 934 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 935 timing_out->pix_clk_100hz = mode_in->clock * 10; 936 } else { 937 timing_out->h_addressable = mode_in->crtc_hdisplay; 938 timing_out->h_total = mode_in->crtc_htotal; 939 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 940 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 941 timing_out->v_total = mode_in->crtc_vtotal; 942 timing_out->v_addressable = mode_in->crtc_vdisplay; 943 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 944 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 945 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 946 } 947 948 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 949 950 stream->out_transfer_func.type = TF_TYPE_PREDEFINED; 951 stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB; 952 953 /* Clamp the HDMI colour depth to what the sink's max TMDS clock 954 * allows. The pixel encoding is fixed by the caller and must not be 955 * changed here: the caller already enumerates YCbCr420 as its own 956 * candidate, so silently switching to it would hide an enumeration 957 * bug and produce a stream the caller never asked to validate. 958 */ 959 if (is_hdmi_ep) 960 adjust_colour_depth_from_display_info(timing_out, info); 961 962 stream->output_color_space = amdgpu_dm_get_output_color_space(timing_out, connector_state); 963 stream->content_type = get_output_content_type(connector_state); 964 } 965 EXPORT_IF_KUNIT(fill_stream_properties_from_drm_display_mode); 966 967 STATIC_IFN_KUNIT void 968 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 969 struct drm_display_mode *dst_mode) 970 { 971 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 972 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 973 dst_mode->crtc_clock = src_mode->crtc_clock; 974 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 975 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 976 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 977 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 978 dst_mode->crtc_htotal = src_mode->crtc_htotal; 979 dst_mode->crtc_hskew = src_mode->crtc_hskew; 980 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 981 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 982 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 983 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 984 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 985 } 986 EXPORT_IF_KUNIT(copy_crtc_timing_for_drm_display_mode); 987 988 STATIC_IFN_KUNIT void 989 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 990 const struct drm_display_mode *native_mode, 991 bool scale_enabled) 992 { 993 if (scale_enabled || ( 994 native_mode->clock == drm_mode->clock && 995 native_mode->htotal == drm_mode->htotal && 996 native_mode->vtotal == drm_mode->vtotal)) { 997 if (native_mode->crtc_clock) 998 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 999 } else { 1000 /* no scaling nor amdgpu inserted, no need to patch */ 1001 } 1002 } 1003 EXPORT_IF_KUNIT(decide_crtc_timing_for_drm_display_mode); 1004 1005 static struct dc_sink * 1006 create_fake_sink(struct drm_device *dev, struct dc_link *link) 1007 { 1008 struct dc_sink_init_data sink_init_data = { 0 }; 1009 struct dc_sink *sink = NULL; 1010 1011 sink_init_data.link = link; 1012 sink_init_data.sink_signal = link->connector_signal; 1013 1014 sink = dc_sink_create(&sink_init_data); 1015 if (!sink) { 1016 drm_err(dev, "Failed to create sink!\n"); 1017 return NULL; 1018 } 1019 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 1020 1021 return sink; 1022 } 1023 1024 /** 1025 * DOC: FreeSync Video 1026 * 1027 * When a userspace application wants to play a video, the content follows a 1028 * standard format definition that usually specifies the FPS for that format. 1029 * The below list illustrates some video format and the expected FPS, 1030 * respectively: 1031 * 1032 * - TV/NTSC (23.976 FPS) 1033 * - Cinema (24 FPS) 1034 * - TV/PAL (25 FPS) 1035 * - TV/NTSC (29.97 FPS) 1036 * - TV/NTSC (30 FPS) 1037 * - Cinema HFR (48 FPS) 1038 * - TV/PAL (50 FPS) 1039 * - Commonly used (60 FPS) 1040 * - Multiples of 24 (48,72,96 FPS) 1041 * 1042 * The list of standards video format is not huge and can be added to the 1043 * connector modeset list beforehand. With that, userspace can leverage 1044 * FreeSync to extends the front porch in order to attain the target refresh 1045 * rate. Such a switch will happen seamlessly, without screen blanking or 1046 * reprogramming of the output in any other way. If the userspace requests a 1047 * modesetting change compatible with FreeSync modes that only differ in the 1048 * refresh rate, DC will skip the full update and avoid blink during the 1049 * transition. For example, the video player can change the modesetting from 1050 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 1051 * causing any display blink. This same concept can be applied to a mode 1052 * setting change. 1053 */ 1054 struct drm_display_mode * 1055 amdgpu_dm_get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 1056 bool use_probed_modes) 1057 { 1058 struct drm_display_mode *m, *m_pref = NULL; 1059 u16 current_refresh, highest_refresh; 1060 struct list_head *list_head = use_probed_modes ? 1061 &aconnector->base.probed_modes : 1062 &aconnector->base.modes; 1063 1064 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1065 return NULL; 1066 1067 if (aconnector->freesync_vid_base.clock != 0) 1068 return &aconnector->freesync_vid_base; 1069 1070 /* Find the preferred mode */ 1071 list_for_each_entry(m, list_head, head) { 1072 if (m->type & DRM_MODE_TYPE_PREFERRED) { 1073 m_pref = m; 1074 break; 1075 } 1076 } 1077 1078 if (!m_pref) { 1079 /* Probably an EDID with no preferred mode. Fallback to first entry */ 1080 m_pref = list_first_entry_or_null( 1081 &aconnector->base.modes, struct drm_display_mode, head); 1082 if (!m_pref) { 1083 drm_dbg_driver(aconnector->base.dev, "No preferred mode found in EDID\n"); 1084 return NULL; 1085 } 1086 } 1087 1088 highest_refresh = drm_mode_vrefresh(m_pref); 1089 1090 /* 1091 * Find the mode with highest refresh rate with same resolution. 1092 * For some monitors, preferred mode is not the mode with highest 1093 * supported refresh rate. 1094 */ 1095 list_for_each_entry(m, list_head, head) { 1096 current_refresh = drm_mode_vrefresh(m); 1097 1098 if (m->hdisplay == m_pref->hdisplay && 1099 m->vdisplay == m_pref->vdisplay && 1100 highest_refresh < current_refresh) { 1101 highest_refresh = current_refresh; 1102 m_pref = m; 1103 } 1104 } 1105 1106 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 1107 return m_pref; 1108 } 1109 EXPORT_IF_KUNIT(amdgpu_dm_get_highest_refresh_rate_mode); 1110 1111 bool amdgpu_dm_is_freesync_video_mode(const struct drm_display_mode *mode, 1112 struct amdgpu_dm_connector *aconnector) 1113 { 1114 struct drm_display_mode *high_mode; 1115 int timing_diff; 1116 1117 high_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 1118 if (!high_mode || !mode) 1119 return false; 1120 1121 timing_diff = high_mode->vtotal - mode->vtotal; 1122 1123 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 1124 high_mode->hdisplay != mode->hdisplay || 1125 high_mode->vdisplay != mode->vdisplay || 1126 high_mode->hsync_start != mode->hsync_start || 1127 high_mode->hsync_end != mode->hsync_end || 1128 high_mode->htotal != mode->htotal || 1129 high_mode->hskew != mode->hskew || 1130 high_mode->vscan != mode->vscan || 1131 high_mode->vsync_start - mode->vsync_start != timing_diff || 1132 high_mode->vsync_end - mode->vsync_end != timing_diff) 1133 return false; 1134 else 1135 return true; 1136 } 1137 EXPORT_IF_KUNIT(amdgpu_dm_is_freesync_video_mode); 1138 1139 #if defined(CONFIG_DRM_AMD_DC_FP) 1140 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 1141 struct dc_sink *sink, struct dc_stream_state *stream, 1142 struct dsc_dec_dpcd_caps *dsc_caps) 1143 { 1144 stream->timing.flags.DSC = 0; 1145 dsc_caps->is_dsc_supported = false; 1146 1147 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 1148 sink->sink_signal == SIGNAL_TYPE_EDP)) { 1149 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) 1150 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 1151 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 1152 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 1153 dsc_caps); 1154 else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 1155 if (aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT && 1156 !aconnector->dsc_settings.dsc_force_disable_passthrough && 1157 aconnector->dc_link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0 && 1158 sink->edid_caps.frl_dsc_support && 1159 sink->edid_caps.max_frl_rate > 0 && 1160 sink->edid_caps.frl_dsc_max_frl_rate > 0) 1161 dc_dsc_parse_dsc_edid(aconnector->dc_link->ctx->dc, &sink->edid_caps, dsc_caps); 1162 else 1163 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 1164 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 1165 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 1166 dsc_caps); 1167 } 1168 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_HDMI_FRL) { 1169 if (sink->edid_caps.frl_dsc_support && 1170 sink->edid_caps.max_frl_rate > 0 && 1171 sink->edid_caps.frl_dsc_max_frl_rate > 0) 1172 dc_dsc_parse_dsc_edid(aconnector->dc_link->ctx->dc, &sink->edid_caps, dsc_caps); 1173 } 1174 } 1175 1176 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 1177 struct dc_sink *sink, struct dc_stream_state *stream, 1178 struct dsc_dec_dpcd_caps *dsc_caps, 1179 uint32_t max_dsc_target_bpp_limit_override) 1180 { 1181 const struct dc_link_settings *verified_link_cap = NULL; 1182 u32 link_bw_in_kbps; 1183 u32 edp_min_bpp_x16, edp_max_bpp_x16; 1184 struct dc *dc = sink->ctx->dc; 1185 struct dc_dsc_bw_range bw_range = {0}; 1186 struct dc_dsc_config dsc_cfg = {0}; 1187 struct dc_dsc_config_options dsc_options = {0}; 1188 1189 dc_dsc_get_default_config_option(dc, &dsc_options); 1190 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 1191 1192 verified_link_cap = dc_link_get_link_cap(stream->link); 1193 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 1194 edp_min_bpp_x16 = 8 * 16; 1195 edp_max_bpp_x16 = 8 * 16; 1196 1197 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 1198 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 1199 1200 if (edp_max_bpp_x16 < edp_min_bpp_x16) 1201 edp_min_bpp_x16 = edp_max_bpp_x16; 1202 1203 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 1204 dc->debug.dsc_min_slice_height_override, 1205 edp_min_bpp_x16, edp_max_bpp_x16, 1206 dsc_caps, 1207 &stream->timing, 1208 dc_link_get_highest_encoding_format(aconnector->dc_link), 1209 &bw_range)) { 1210 1211 if (bw_range.max_kbps < link_bw_in_kbps) { 1212 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 1213 dsc_caps, 1214 &dsc_options, 1215 0, 1216 &stream->timing, 1217 dc_link_get_highest_encoding_format(aconnector->dc_link), 1218 &dsc_cfg)) { 1219 stream->timing.dsc_cfg = dsc_cfg; 1220 stream->timing.flags.DSC = 1; 1221 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 1222 } 1223 return; 1224 } 1225 } 1226 1227 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 1228 dsc_caps, 1229 &dsc_options, 1230 link_bw_in_kbps, 1231 &stream->timing, 1232 dc_link_get_highest_encoding_format(aconnector->dc_link), 1233 &dsc_cfg)) { 1234 stream->timing.dsc_cfg = dsc_cfg; 1235 stream->timing.flags.DSC = 1; 1236 } 1237 } 1238 1239 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 1240 struct dc_sink *sink, struct dc_stream_state *stream, 1241 struct dsc_dec_dpcd_caps *dsc_caps) 1242 { 1243 struct drm_connector *drm_connector = &aconnector->base; 1244 u32 link_bandwidth_kbps; 1245 struct dc *dc = sink->ctx->dc; 1246 const struct dc_hdmi_frl_link_settings *frl_verified_link_cap = NULL; 1247 u32 converter_bw_in_kbps; 1248 u32 sink_bw_in_kbps; 1249 u32 dsc_sink_bw_in_kbps; 1250 u32 max_supported_bw_in_kbps, timing_bw_in_kbps; 1251 u32 dsc_max_supported_bw_in_kbps; 1252 u32 max_dsc_target_bpp_limit_override = 1253 drm_connector->display_info.max_dsc_bpp; 1254 struct dc_dsc_config_options dsc_options = {0}; 1255 1256 if (!aconnector->dc_link) 1257 return; 1258 1259 dc_dsc_get_default_config_option(dc, &dsc_options); 1260 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 1261 1262 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 1263 dc_link_get_link_cap(aconnector->dc_link)); 1264 1265 /* Set DSC policy according to dsc_clock_en */ 1266 dc_dsc_policy_set_enable_dsc_when_not_needed( 1267 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 1268 1269 if (sink->sink_signal == SIGNAL_TYPE_EDP && 1270 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 1271 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 1272 1273 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 1274 1275 } else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 1276 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 1277 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 1278 dsc_caps, 1279 &dsc_options, 1280 link_bandwidth_kbps, 1281 &stream->timing, 1282 dc_link_get_highest_encoding_format(aconnector->dc_link), 1283 &stream->timing.dsc_cfg)) { 1284 stream->timing.flags.DSC = 1; 1285 drm_dbg_driver(drm_connector->dev, "%s: SST_DSC [%s] DSC is selected from SST RX\n", 1286 __func__, drm_connector->name); 1287 } 1288 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 1289 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 1290 dc_link_get_highest_encoding_format(aconnector->dc_link)); 1291 converter_bw_in_kbps = aconnector->dc_link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps; 1292 sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(dc, sink->edid_caps.max_frl_rate); 1293 dsc_sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(dc, sink->edid_caps.frl_dsc_max_frl_rate); 1294 1295 if (dsc_caps->is_frl) { 1296 max_supported_bw_in_kbps = min(link_bandwidth_kbps, converter_bw_in_kbps); 1297 max_supported_bw_in_kbps = min(max_supported_bw_in_kbps, sink_bw_in_kbps); 1298 dsc_max_supported_bw_in_kbps = min(max_supported_bw_in_kbps, dsc_sink_bw_in_kbps); 1299 } else { 1300 max_supported_bw_in_kbps = link_bandwidth_kbps; 1301 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 1302 } 1303 1304 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 1305 max_supported_bw_in_kbps > 0 && 1306 dsc_max_supported_bw_in_kbps > 0) 1307 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 1308 dsc_caps, 1309 &dsc_options, 1310 dsc_max_supported_bw_in_kbps, 1311 &stream->timing, 1312 dc_link_get_highest_encoding_format(aconnector->dc_link), 1313 &stream->timing.dsc_cfg)) { 1314 stream->timing.flags.DSC = 1; 1315 drm_dbg_driver(drm_connector->dev, "%s: SST_DSC [%s] DSC is selected from %s\n", 1316 __func__, drm_connector->name, 1317 (dsc_caps->is_frl == 1) ? "HDMI FRL RX" : "DP-HDMI PCON"); 1318 } 1319 } 1320 } else if (sink->sink_signal == SIGNAL_TYPE_HDMI_FRL) { 1321 struct dc_dsc_policy dsc_policy = {0}; 1322 1323 frl_verified_link_cap = dc_link_get_frl_link_cap(stream->link); 1324 if (frl_verified_link_cap->frl_link_rate != HDMI_FRL_LINK_RATE_DISABLE && 1325 aconnector->dc_link->frl_flags.force_frl_dsc) { 1326 dc_dsc_policy_set_enable_dsc_when_not_needed(true); 1327 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link)); 1328 } 1329 1330 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, DC_LINK_ENCODING_HDMI_FRL); 1331 link_bandwidth_kbps = dc_link_frl_bandwidth_kbps(stream->link, frl_verified_link_cap->frl_link_rate); 1332 dsc_sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(dc, sink->edid_caps.frl_dsc_max_frl_rate); 1333 1334 if ((timing_bw_in_kbps > link_bandwidth_kbps && dsc_sink_bw_in_kbps > 0) || 1335 (dsc_policy.enable_dsc_when_not_needed || dsc_options.force_dsc_when_not_needed)) { 1336 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 1337 dsc_caps, 1338 &dsc_options, 1339 dsc_sink_bw_in_kbps, 1340 &stream->timing, 1341 dc_link_get_highest_encoding_format(aconnector->dc_link), 1342 &stream->timing.dsc_cfg)) { 1343 stream->timing.flags.DSC = 1; 1344 drm_dbg_driver(drm_connector->dev, "%s: HDMI_FRL_DSC [%s] DSC is selected from HDMI FRL RX\n", 1345 __func__, drm_connector->name); 1346 } 1347 } 1348 } 1349 1350 /* Overwrite the stream flag if DSC is enabled through debugfs */ 1351 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 1352 stream->timing.flags.DSC = 1; 1353 1354 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 1355 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 1356 1357 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 1358 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 1359 1360 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 1361 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 1362 } 1363 #endif 1364 1365 void amdgpu_dm_update_stream_scaling_settings(struct drm_device *dev, 1366 const struct drm_display_mode *mode, 1367 const struct dm_connector_state *dm_state, 1368 struct dc_stream_state *stream) 1369 { 1370 enum amdgpu_rmx_type rmx_type; 1371 1372 struct rect src = { 0 }; /* viewport in composition space*/ 1373 struct rect dst = { 0 }; /* stream addressable area */ 1374 1375 /* no mode. nothing to be done */ 1376 if (!mode) 1377 return; 1378 1379 /* Full screen scaling by default */ 1380 src.width = mode->hdisplay; 1381 src.height = mode->vdisplay; 1382 dst.width = stream->timing.h_addressable; 1383 dst.height = stream->timing.v_addressable; 1384 1385 if (dm_state) { 1386 rmx_type = dm_state->scaling; 1387 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 1388 if (src.width * dst.height < 1389 src.height * dst.width) { 1390 /* height needs less upscaling/more downscaling */ 1391 dst.width = src.width * 1392 dst.height / src.height; 1393 } else { 1394 /* width needs less upscaling/more downscaling */ 1395 dst.height = src.height * 1396 dst.width / src.width; 1397 } 1398 } else if (rmx_type == RMX_CENTER) { 1399 dst = src; 1400 } 1401 1402 dst.x = (stream->timing.h_addressable - dst.width) / 2; 1403 dst.y = (stream->timing.v_addressable - dst.height) / 2; 1404 1405 if (dm_state->underscan_enable) { 1406 dst.x += dm_state->underscan_hborder / 2; 1407 dst.y += dm_state->underscan_vborder / 2; 1408 dst.width -= dm_state->underscan_hborder; 1409 dst.height -= dm_state->underscan_vborder; 1410 } 1411 } 1412 1413 stream->src = src; 1414 stream->dst = dst; 1415 1416 drm_dbg_kms(dev, "Destination Rectangle x:%d y:%d width:%d height:%d\n", 1417 dst.x, dst.y, dst.width, dst.height); 1418 1419 } 1420 EXPORT_IF_KUNIT(amdgpu_dm_update_stream_scaling_settings); 1421 1422 STATIC_IFN_KUNIT struct dc_stream_state * 1423 create_stream_for_sink(struct drm_connector *connector, 1424 const struct drm_display_mode *drm_mode, 1425 const struct dm_connector_state *dm_state, 1426 const struct dc_stream_state *old_stream, 1427 int requested_bpc, 1428 enum dc_pixel_encoding requested_encoding, 1429 bool is_hdmi_ep) 1430 { 1431 struct drm_device *dev = connector->dev; 1432 struct amdgpu_dm_connector *aconnector = NULL; 1433 struct drm_display_mode *preferred_mode = NULL; 1434 const struct drm_connector_state *con_state = &dm_state->base; 1435 struct dc_stream_state *stream = NULL; 1436 struct drm_display_mode mode; 1437 struct drm_display_mode saved_mode; 1438 struct drm_display_mode *freesync_mode = NULL; 1439 bool native_mode_found = false; 1440 bool recalculate_timing = false; 1441 bool scale = dm_state->scaling != RMX_OFF; 1442 int mode_refresh; 1443 int preferred_refresh = 0; 1444 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 1445 #if defined(CONFIG_DRM_AMD_DC_FP) 1446 struct dsc_dec_dpcd_caps dsc_caps = {0}; 1447 #endif 1448 struct dc_link *link = NULL; 1449 struct dc_sink *sink = NULL; 1450 1451 drm_mode_init(&mode, drm_mode); 1452 memset(&saved_mode, 0, sizeof(saved_mode)); 1453 1454 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) { 1455 aconnector = NULL; 1456 aconnector = to_amdgpu_dm_connector(connector); 1457 link = aconnector->dc_link; 1458 } else { 1459 struct drm_writeback_connector *wbcon = NULL; 1460 struct amdgpu_dm_wb_connector *dm_wbcon = NULL; 1461 1462 wbcon = drm_connector_to_writeback(connector); 1463 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon); 1464 link = dm_wbcon->link; 1465 } 1466 1467 if (!aconnector || !aconnector->dc_sink) { 1468 sink = create_fake_sink(dev, link); 1469 if (!sink) 1470 return stream; 1471 1472 } else { 1473 sink = aconnector->dc_sink; 1474 dc_sink_retain(sink); 1475 } 1476 1477 stream = dc_create_stream_for_sink(sink); 1478 1479 if (stream == NULL) { 1480 drm_err(dev, "Failed to create stream for sink!\n"); 1481 goto finish; 1482 } 1483 1484 /* We leave this NULL for writeback connectors */ 1485 stream->dm_stream_context = aconnector; 1486 1487 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 1488 connector->display_info.hdmi.scdc.scrambling.low_rates; 1489 1490 list_for_each_entry(preferred_mode, &connector->modes, head) { 1491 /* Search for preferred mode */ 1492 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 1493 native_mode_found = true; 1494 break; 1495 } 1496 } 1497 if (!native_mode_found) 1498 preferred_mode = list_first_entry_or_null( 1499 &connector->modes, 1500 struct drm_display_mode, 1501 head); 1502 1503 mode_refresh = drm_mode_vrefresh(&mode); 1504 1505 if (preferred_mode == NULL) { 1506 /* 1507 * This may not be an error, the use case is when we have no 1508 * usermode calls to reset and set mode upon hotplug. In this 1509 * case, we call set mode ourselves to restore the previous mode 1510 * and the modelist may not be filled in time. 1511 */ 1512 drm_dbg_driver(dev, "No preferred mode found\n"); 1513 } else if (aconnector) { 1514 recalculate_timing = amdgpu_freesync_vid_mode && 1515 amdgpu_dm_is_freesync_video_mode(&mode, aconnector); 1516 if (recalculate_timing) { 1517 freesync_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 1518 drm_mode_copy(&saved_mode, &mode); 1519 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio; 1520 drm_mode_copy(&mode, freesync_mode); 1521 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio; 1522 } else { 1523 decide_crtc_timing_for_drm_display_mode( 1524 &mode, preferred_mode, scale); 1525 1526 preferred_refresh = drm_mode_vrefresh(preferred_mode); 1527 } 1528 } 1529 1530 if (recalculate_timing) 1531 drm_mode_set_crtcinfo(&saved_mode, 0); 1532 1533 /* 1534 * If scaling is enabled and refresh rate didn't change 1535 * we copy the vic and polarities of the old timings 1536 */ 1537 if (!scale || mode_refresh != preferred_refresh) 1538 fill_stream_properties_from_drm_display_mode( 1539 stream, &mode, connector, con_state, NULL, 1540 requested_bpc, requested_encoding, is_hdmi_ep); 1541 else 1542 fill_stream_properties_from_drm_display_mode( 1543 stream, &mode, connector, con_state, old_stream, 1544 requested_bpc, requested_encoding, is_hdmi_ep); 1545 1546 /* The rest isn't needed for writeback connectors */ 1547 if (!aconnector) 1548 goto finish; 1549 1550 if (aconnector->timing_changed) { 1551 drm_dbg(aconnector->base.dev, 1552 "overriding timing for automated test, bpc %d, changing to %d\n", 1553 stream->timing.display_color_depth, 1554 aconnector->timing_requested->display_color_depth); 1555 stream->timing = *aconnector->timing_requested; 1556 } 1557 1558 #if defined(CONFIG_DRM_AMD_DC_FP) 1559 /* SST DSC determination policy */ 1560 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 1561 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 1562 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 1563 #endif 1564 1565 amdgpu_dm_update_stream_scaling_settings(dev, &mode, dm_state, stream); 1566 1567 amdgpu_dm_fill_audio_info( 1568 &stream->audio_info, 1569 connector, 1570 sink); 1571 1572 update_stream_signal(stream, sink); 1573 1574 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 1575 stream->signal == SIGNAL_TYPE_HDMI_FRL) 1576 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false); 1577 1578 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1579 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 1580 stream->signal == SIGNAL_TYPE_EDP) { 1581 const struct dc_edid_caps *edid_caps; 1582 unsigned int disable_colorimetry = 0; 1583 1584 if (aconnector->dc_sink) { 1585 edid_caps = &aconnector->dc_sink->edid_caps; 1586 disable_colorimetry = edid_caps->panel_patch.disable_colorimetry; 1587 } 1588 1589 /* 1590 * should decide stream support vsc sdp colorimetry capability 1591 * before building vsc info packet 1592 */ 1593 stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && 1594 stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED && 1595 !disable_colorimetry; 1596 1597 if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) 1598 tf = TRANSFER_FUNC_GAMMA_22; 1599 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 1600 aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 1601 1602 } 1603 finish: 1604 dc_sink_release(sink); 1605 1606 return stream; 1607 } 1608 EXPORT_IF_KUNIT(create_stream_for_sink); 1609 1610 /** 1611 * amdgpu_dm_connector_poll - Poll a connector to see if it's connected to a display 1612 * @aconnector: DM connector to poll (owns @base drm_connector and @dc_link) 1613 * @force: if true, force polling even when DAC load detection was used 1614 * 1615 * Used for connectors that don't support HPD (hotplug detection) to 1616 * periodically check whether the connector is connected to a display. 1617 * 1618 * When connection was determined via DAC load detection, we avoid 1619 * re-running it on normal polls to prevent visible glitches, unless 1620 * @force is set. 1621 * 1622 * Return: The probed connector status (connected/disconnected/unknown). 1623 */ 1624 STATIC_IFN_KUNIT enum drm_connector_status 1625 amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force) 1626 { 1627 struct drm_connector *connector = &aconnector->base; 1628 struct drm_device *dev = connector->dev; 1629 struct amdgpu_device *adev = drm_to_adev(dev); 1630 struct dc_link *link = aconnector->dc_link; 1631 enum dc_connection_type conn_type = dc_connection_none; 1632 enum drm_connector_status status = connector_status_disconnected; 1633 1634 /* When we determined the connection using DAC load detection, 1635 * do NOT poll the connector do detect disconnect because 1636 * that would run DAC load detection again which can cause 1637 * visible visual glitches. 1638 * 1639 * Only allow to poll such a connector again when forcing. 1640 */ 1641 if (!force && link->local_sink && link->type == dc_connection_analog_load) 1642 return connector->status; 1643 1644 mutex_lock(&aconnector->hpd_lock); 1645 1646 if (dc_link_detect_connection_type(aconnector->dc_link, &conn_type) && 1647 conn_type != dc_connection_none) { 1648 mutex_lock(&adev->dm.dc_lock); 1649 1650 /* Only call full link detection when a sink isn't created yet, 1651 * ie. just when the display is plugged in, otherwise we risk flickering. 1652 */ 1653 if (link->local_sink || 1654 dc_link_detect(link, DETECT_REASON_HPD)) 1655 status = connector_status_connected; 1656 1657 mutex_unlock(&adev->dm.dc_lock); 1658 } 1659 1660 if (connector->status != status) { 1661 if (status == connector_status_disconnected) { 1662 if (link->local_sink) 1663 dc_sink_release(link->local_sink); 1664 1665 link->local_sink = NULL; 1666 link->dpcd_sink_count = 0; 1667 link->type = dc_connection_none; 1668 } 1669 1670 amdgpu_dm_update_connector_after_detect(aconnector); 1671 } 1672 1673 mutex_unlock(&aconnector->hpd_lock); 1674 return status; 1675 } 1676 EXPORT_IF_KUNIT(amdgpu_dm_connector_poll); 1677 1678 /* 1679 * Apple Studio Display exposes two SST DP links for a 2x1 tiled panel. 1680 * The primary tile advertises the full 5120x2880 mode (with DSC on the 1681 * bandwidth-sufficient link) while the secondary carries a per-tile 1682 * 2560x2880 timing on a insufficient bandwidth link. Hide the secondary 1683 * connector from userspace so compositors configure a single 5K stream 1684 * on the primary link only. 1685 */ 1686 static bool amdgpu_dm_hide_secondary_tile_from_userspace(struct drm_connector *connector) 1687 { 1688 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1689 1690 if (!aconnector->dc_sink) 1691 return false; 1692 1693 if (!aconnector->dc_sink->edid_caps.panel_patch.disable_second_tile) 1694 return false; 1695 1696 drm_edid_connector_update(connector, aconnector->drm_edid); 1697 1698 if (!connector->has_tile) 1699 return false; 1700 1701 if (!connector->tile_h_loc && !connector->tile_v_loc) 1702 return false; 1703 1704 drm_dbg_kms(connector->dev, 1705 "[CONNECTOR:%d:%s] hiding secondary Apple Studio Display tile from userspace\n", 1706 connector->base.id, connector->name); 1707 1708 return true; 1709 } 1710 1711 /** 1712 * amdgpu_dm_connector_detect() - Detect whether a DRM connector is connected to a display 1713 * 1714 * A connector is considered connected when it has a sink that is not NULL. 1715 * For connectors that support HPD (hotplug detection), the connection is 1716 * handled in the HPD interrupt. 1717 * For connectors that may not support HPD, such as analog connectors, 1718 * DRM will call this function repeatedly to poll them. 1719 * 1720 * Notes: 1721 * 1. This interface is NOT called in context of HPD irq. 1722 * 2. This interface *is called* in context of user-mode ioctl. Which 1723 * makes it a bad place for *any* MST-related activity. 1724 * 1725 * @connector: The DRM connector we are checking. We convert it to 1726 * amdgpu_dm_connector so we can read the DC link and state. 1727 * @force: If true, do a full detect again. This is used even when 1728 * a lighter check would normally be used to avoid flicker. 1729 * 1730 * Return: The connector status (connected, disconnected, or unknown). 1731 * 1732 */ 1733 STATIC_IFN_KUNIT enum drm_connector_status 1734 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 1735 { 1736 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1737 1738 update_subconnector_property(aconnector); 1739 1740 if (aconnector->base.force == DRM_FORCE_ON || 1741 aconnector->base.force == DRM_FORCE_ON_DIGITAL) 1742 return connector_status_connected; 1743 else if (aconnector->base.force == DRM_FORCE_OFF) 1744 return connector_status_disconnected; 1745 1746 /* Poll analog connectors and only when either 1747 * disconnected or connected to an analog display. 1748 */ 1749 if (drm_kms_helper_is_poll_worker() && 1750 dc_connector_supports_analog(aconnector->dc_link->link_id.id) && 1751 (!aconnector->dc_sink || aconnector->dc_sink->edid_caps.analog)) 1752 return amdgpu_dm_connector_poll(aconnector, force); 1753 1754 if (amdgpu_dm_hide_secondary_tile_from_userspace(connector)) 1755 return connector_status_disconnected; 1756 1757 return (aconnector->dc_sink ? connector_status_connected : 1758 connector_status_disconnected); 1759 } 1760 EXPORT_IF_KUNIT(amdgpu_dm_connector_detect); 1761 1762 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 1763 struct drm_connector_state *connector_state, 1764 struct drm_property *property, 1765 uint64_t val) 1766 { 1767 struct drm_device *dev = connector->dev; 1768 struct amdgpu_device *adev = drm_to_adev(dev); 1769 struct dm_connector_state *dm_old_state = 1770 to_dm_connector_state(connector->state); 1771 struct dm_connector_state *dm_new_state = 1772 to_dm_connector_state(connector_state); 1773 1774 int ret = -EINVAL; 1775 1776 if (property == dev->mode_config.scaling_mode_property) { 1777 enum amdgpu_rmx_type rmx_type; 1778 1779 switch (val) { 1780 case DRM_MODE_SCALE_CENTER: 1781 rmx_type = RMX_CENTER; 1782 break; 1783 case DRM_MODE_SCALE_ASPECT: 1784 rmx_type = RMX_ASPECT; 1785 break; 1786 case DRM_MODE_SCALE_FULLSCREEN: 1787 rmx_type = RMX_FULL; 1788 break; 1789 case DRM_MODE_SCALE_NONE: 1790 default: 1791 rmx_type = RMX_OFF; 1792 break; 1793 } 1794 1795 if (dm_old_state->scaling == rmx_type) 1796 return 0; 1797 1798 dm_new_state->scaling = rmx_type; 1799 ret = 0; 1800 } else if (property == adev->mode_info.underscan_hborder_property) { 1801 dm_new_state->underscan_hborder = val; 1802 ret = 0; 1803 } else if (property == adev->mode_info.underscan_vborder_property) { 1804 dm_new_state->underscan_vborder = val; 1805 ret = 0; 1806 } else if (property == adev->mode_info.underscan_property) { 1807 dm_new_state->underscan_enable = val; 1808 ret = 0; 1809 } else if (property == adev->mode_info.abm_level_property) { 1810 switch (val) { 1811 case ABM_SYSFS_CONTROL: 1812 dm_new_state->abm_sysfs_forbidden = false; 1813 break; 1814 case ABM_LEVEL_OFF: 1815 dm_new_state->abm_sysfs_forbidden = true; 1816 dm_new_state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 1817 break; 1818 default: 1819 dm_new_state->abm_sysfs_forbidden = true; 1820 dm_new_state->abm_level = val; 1821 } 1822 ret = 0; 1823 } 1824 1825 return ret; 1826 } 1827 EXPORT_IF_KUNIT(amdgpu_dm_connector_atomic_set_property); 1828 1829 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 1830 const struct drm_connector_state *state, 1831 struct drm_property *property, 1832 uint64_t *val) 1833 { 1834 struct drm_device *dev = connector->dev; 1835 struct amdgpu_device *adev = drm_to_adev(dev); 1836 struct dm_connector_state *dm_state = 1837 to_dm_connector_state(state); 1838 int ret = -EINVAL; 1839 1840 if (property == dev->mode_config.scaling_mode_property) { 1841 switch (dm_state->scaling) { 1842 case RMX_CENTER: 1843 *val = DRM_MODE_SCALE_CENTER; 1844 break; 1845 case RMX_ASPECT: 1846 *val = DRM_MODE_SCALE_ASPECT; 1847 break; 1848 case RMX_FULL: 1849 *val = DRM_MODE_SCALE_FULLSCREEN; 1850 break; 1851 case RMX_OFF: 1852 default: 1853 *val = DRM_MODE_SCALE_NONE; 1854 break; 1855 } 1856 ret = 0; 1857 } else if (property == adev->mode_info.underscan_hborder_property) { 1858 *val = dm_state->underscan_hborder; 1859 ret = 0; 1860 } else if (property == adev->mode_info.underscan_vborder_property) { 1861 *val = dm_state->underscan_vborder; 1862 ret = 0; 1863 } else if (property == adev->mode_info.underscan_property) { 1864 *val = dm_state->underscan_enable; 1865 ret = 0; 1866 } else if (property == adev->mode_info.abm_level_property) { 1867 if (!dm_state->abm_sysfs_forbidden) 1868 *val = ABM_SYSFS_CONTROL; 1869 else 1870 *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ? 1871 dm_state->abm_level : 0; 1872 ret = 0; 1873 } 1874 1875 return ret; 1876 } 1877 EXPORT_IF_KUNIT(amdgpu_dm_connector_atomic_get_property); 1878 1879 STATIC_IFN_KUNIT void amdgpu_dm_connector_unregister(struct drm_connector *connector) 1880 { 1881 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 1882 1883 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) 1884 sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); 1885 1886 cec_notifier_conn_unregister(amdgpu_dm_connector->notifier); 1887 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 1888 } 1889 EXPORT_IF_KUNIT(amdgpu_dm_connector_unregister); 1890 1891 STATIC_IFN_KUNIT void amdgpu_dm_connector_destroy(struct drm_connector *connector) 1892 { 1893 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1894 struct amdgpu_device *adev = drm_to_adev(connector->dev); 1895 struct amdgpu_display_manager *dm = &adev->dm; 1896 1897 /* 1898 * Call only if mst_mgr was initialized before since it's not done 1899 * for all connector types. 1900 */ 1901 if (aconnector->mst_mgr.dev) 1902 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 1903 1904 /* Cancel and flush any pending HDMI HPD debounce work */ 1905 if (aconnector->hdmi_hpd_debounce_delay_ms) { 1906 cancel_delayed_work_sync(&aconnector->hdmi_hpd_debounce_work); 1907 if (aconnector->hdmi_prev_sink) { 1908 dc_sink_release(aconnector->hdmi_prev_sink); 1909 aconnector->hdmi_prev_sink = NULL; 1910 } 1911 } 1912 1913 if (aconnector->bl_idx != -1) { 1914 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 1915 dm->backlight_dev[aconnector->bl_idx] = NULL; 1916 } 1917 1918 if (aconnector->dc_em_sink) 1919 dc_sink_release(aconnector->dc_em_sink); 1920 aconnector->dc_em_sink = NULL; 1921 if (aconnector->dc_sink) 1922 dc_sink_release(aconnector->dc_sink); 1923 aconnector->dc_sink = NULL; 1924 1925 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 1926 drm_connector_unregister(connector); 1927 drm_connector_cleanup(connector); 1928 kfree(aconnector->dm_dp_aux.aux.name); 1929 1930 kfree(connector); 1931 } 1932 EXPORT_IF_KUNIT(amdgpu_dm_connector_destroy); 1933 1934 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 1935 { 1936 struct dm_connector_state *old_state = 1937 to_dm_connector_state(connector->state); 1938 struct dm_connector_state *state; 1939 1940 state = kzalloc_obj(*state); 1941 if (!state) 1942 return; 1943 1944 if (connector->state) 1945 __drm_atomic_helper_connector_destroy_state(connector->state); 1946 1947 kfree(old_state); 1948 1949 __drm_atomic_helper_connector_reset(connector, &state->base); 1950 1951 state->scaling = RMX_OFF; 1952 state->underscan_enable = false; 1953 state->underscan_hborder = 0; 1954 state->underscan_vborder = 0; 1955 state->base.max_requested_bpc = 8; 1956 state->vcpi_slots = 0; 1957 state->pbn = 0; 1958 1959 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1960 if (amdgpu_dm_abm_level <= 0) 1961 state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 1962 else 1963 state->abm_level = amdgpu_dm_abm_level; 1964 } 1965 } 1966 EXPORT_IF_KUNIT(amdgpu_dm_connector_funcs_reset); 1967 1968 struct drm_connector_state * 1969 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 1970 { 1971 struct dm_connector_state *state = 1972 to_dm_connector_state(connector->state); 1973 1974 struct dm_connector_state *new_state = 1975 kmemdup(state, sizeof(*state), GFP_KERNEL); 1976 1977 if (!new_state) 1978 return NULL; 1979 1980 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 1981 1982 new_state->freesync_capable = state->freesync_capable; 1983 new_state->abm_level = state->abm_level; 1984 new_state->scaling = state->scaling; 1985 new_state->underscan_enable = state->underscan_enable; 1986 new_state->underscan_hborder = state->underscan_hborder; 1987 new_state->underscan_vborder = state->underscan_vborder; 1988 new_state->vcpi_slots = state->vcpi_slots; 1989 new_state->pbn = state->pbn; 1990 return &new_state->base; 1991 } 1992 EXPORT_IF_KUNIT(amdgpu_dm_connector_atomic_duplicate_state); 1993 1994 STATIC_IFN_KUNIT int 1995 amdgpu_dm_connector_late_register(struct drm_connector *connector) 1996 { 1997 struct amdgpu_dm_connector *amdgpu_dm_connector = 1998 to_amdgpu_dm_connector(connector); 1999 int r; 2000 2001 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) { 2002 r = sysfs_create_group(&connector->kdev->kobj, 2003 &amdgpu_group); 2004 if (r) 2005 return r; 2006 } 2007 2008 amdgpu_dm_register_backlight_device(amdgpu_dm_connector); 2009 2010 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 2011 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 2012 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 2013 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 2014 if (r) 2015 return r; 2016 } 2017 2018 #if defined(CONFIG_DEBUG_FS) 2019 connector_debugfs_init(amdgpu_dm_connector); 2020 #endif 2021 2022 return 0; 2023 } 2024 EXPORT_IF_KUNIT(amdgpu_dm_connector_late_register); 2025 2026 STATIC_IFN_KUNIT void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) 2027 { 2028 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2029 struct dc_link *dc_link = aconnector->dc_link; 2030 struct dc_sink *dc_em_sink = aconnector->dc_em_sink; 2031 const struct drm_edid *drm_edid; 2032 struct i2c_adapter *ddc; 2033 struct drm_device *dev = connector->dev; 2034 2035 if (dc_link && dc_link->aux_mode) 2036 ddc = &aconnector->dm_dp_aux.aux.ddc; 2037 else 2038 ddc = &aconnector->i2c->base; 2039 2040 drm_edid = drm_edid_read_ddc(connector, ddc); 2041 drm_edid_connector_update(connector, drm_edid); 2042 if (!drm_edid) { 2043 drm_err(dev, "No EDID found on connector: %s.\n", connector->name); 2044 return; 2045 } 2046 2047 aconnector->drm_edid = drm_edid; 2048 /* Update emulated (virtual) sink's EDID */ 2049 if (dc_em_sink && dc_link) { 2050 /* FIXME: Get rid of drm_edid_raw() */ 2051 const struct edid *edid = drm_edid_raw(drm_edid); 2052 2053 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); 2054 memmove(dc_em_sink->dc_edid.raw_edid, edid, 2055 (edid->extensions + 1) * EDID_LENGTH); 2056 dm_helpers_parse_edid_caps( 2057 dc_link, 2058 &dc_em_sink->dc_edid, 2059 &dc_em_sink->edid_caps); 2060 } 2061 } 2062 EXPORT_IF_KUNIT(amdgpu_dm_connector_funcs_force); 2063 2064 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 2065 .reset = amdgpu_dm_connector_funcs_reset, 2066 .detect = amdgpu_dm_connector_detect, 2067 .fill_modes = drm_helper_probe_single_connector_modes, 2068 .destroy = amdgpu_dm_connector_destroy, 2069 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 2070 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2071 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 2072 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 2073 .late_register = amdgpu_dm_connector_late_register, 2074 .early_unregister = amdgpu_dm_connector_unregister, 2075 .force = amdgpu_dm_connector_funcs_force 2076 }; 2077 2078 static int get_modes(struct drm_connector *connector) 2079 { 2080 return amdgpu_dm_connector_get_modes(connector); 2081 } 2082 2083 STATIC_IFN_KUNIT void create_eml_sink(struct amdgpu_dm_connector *aconnector) 2084 { 2085 struct drm_connector *connector = &aconnector->base; 2086 struct dc_link *dc_link = aconnector->dc_link; 2087 struct dc_sink_init_data init_params = { 2088 .link = aconnector->dc_link, 2089 .sink_signal = SIGNAL_TYPE_VIRTUAL 2090 }; 2091 const struct drm_edid *drm_edid; 2092 const struct edid *edid; 2093 struct i2c_adapter *ddc; 2094 2095 if (dc_link && dc_link->aux_mode) 2096 ddc = &aconnector->dm_dp_aux.aux.ddc; 2097 else 2098 ddc = &aconnector->i2c->base; 2099 2100 drm_edid = drm_edid_read_ddc(connector, ddc); 2101 drm_edid_connector_update(connector, drm_edid); 2102 if (!drm_edid) { 2103 drm_err(connector->dev, "No EDID found on connector: %s.\n", connector->name); 2104 return; 2105 } 2106 2107 if (connector->display_info.is_hdmi) 2108 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 2109 2110 aconnector->drm_edid = drm_edid; 2111 2112 /* FIXME: Get rid of drm_edid_raw() */ 2113 edid = drm_edid_raw(drm_edid); 2114 aconnector->dc_em_sink = dc_link_add_remote_sink( 2115 aconnector->dc_link, 2116 (uint8_t *)edid, 2117 (edid->extensions + 1) * EDID_LENGTH, 2118 &init_params); 2119 2120 if (aconnector->base.force == DRM_FORCE_ON) { 2121 aconnector->dc_sink = aconnector->dc_link->local_sink ? 2122 aconnector->dc_link->local_sink : 2123 aconnector->dc_em_sink; 2124 if (aconnector->dc_sink) 2125 dc_sink_retain(aconnector->dc_sink); 2126 } 2127 } 2128 EXPORT_IF_KUNIT(create_eml_sink); 2129 2130 STATIC_IFN_KUNIT void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 2131 { 2132 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 2133 2134 /* 2135 * In case of headless boot with force on for DP managed connector 2136 * Those settings have to be != 0 to get initial modeset 2137 */ 2138 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 2139 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 2140 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 2141 } 2142 2143 create_eml_sink(aconnector); 2144 } 2145 EXPORT_IF_KUNIT(handle_edid_mgmt); 2146 2147 STATIC_IFN_KUNIT enum dc_status dm_validate_stream_and_context(struct dc *dc, 2148 struct dc_stream_state *stream) 2149 { 2150 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 2151 struct dc_plane_state *dc_plane_state = NULL; 2152 struct dc_state *dc_state = NULL; 2153 2154 if (!stream) 2155 goto cleanup; 2156 2157 dc_plane_state = dc_create_plane_state(dc); 2158 if (!dc_plane_state) 2159 goto cleanup; 2160 2161 dc_state = dc_state_create(dc, NULL); 2162 if (!dc_state) 2163 goto cleanup; 2164 2165 /* populate stream to plane */ 2166 dc_plane_state->src_rect.height = stream->src.height; 2167 dc_plane_state->src_rect.width = stream->src.width; 2168 dc_plane_state->dst_rect.height = stream->src.height; 2169 dc_plane_state->dst_rect.width = stream->src.width; 2170 dc_plane_state->clip_rect.height = stream->src.height; 2171 dc_plane_state->clip_rect.width = stream->src.width; 2172 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 2173 dc_plane_state->plane_size.surface_size.height = stream->src.height; 2174 dc_plane_state->plane_size.surface_size.width = stream->src.width; 2175 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 2176 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 2177 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2178 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 2179 dc_plane_state->rotation = ROTATION_ANGLE_0; 2180 dc_plane_state->is_tiling_rotated = false; 2181 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 2182 2183 dc_result = dc_validate_stream(dc, stream); 2184 if (dc_result == DC_OK) 2185 dc_result = dc_validate_plane(dc, dc_plane_state); 2186 2187 if (dc_result == DC_OK) 2188 dc_result = dc_state_add_stream(dc, dc_state, stream); 2189 2190 if (dc_result == DC_OK && !dc_state_add_plane( 2191 dc, 2192 stream, 2193 dc_plane_state, 2194 dc_state)) 2195 dc_result = DC_FAIL_ATTACH_SURFACES; 2196 2197 if (dc_result == DC_OK) 2198 dc_result = dc_validate_global_state(dc, dc_state, DC_VALIDATE_MODE_ONLY); 2199 2200 cleanup: 2201 if (dc_state) 2202 dc_state_release(dc_state); 2203 2204 if (dc_plane_state) 2205 dc_plane_state_release(dc_plane_state); 2206 2207 return dc_result; 2208 } 2209 EXPORT_IF_KUNIT(dm_validate_stream_and_context); 2210 2211 static enum dc_status 2212 dm_validate_stream_color_format(const struct drm_connector_state *drm_state, 2213 const struct dc_stream_state *stream) 2214 { 2215 enum dc_pixel_encoding encoding; 2216 2217 if (!drm_state->color_format) 2218 return DC_OK; 2219 2220 switch (drm_state->color_format) { 2221 case DRM_CONNECTOR_COLOR_FORMAT_AUTO: 2222 case DRM_CONNECTOR_COLOR_FORMAT_RGB444: 2223 encoding = PIXEL_ENCODING_RGB; 2224 break; 2225 case DRM_CONNECTOR_COLOR_FORMAT_YCBCR444: 2226 encoding = PIXEL_ENCODING_YCBCR444; 2227 break; 2228 case DRM_CONNECTOR_COLOR_FORMAT_YCBCR422: 2229 encoding = PIXEL_ENCODING_YCBCR422; 2230 break; 2231 case DRM_CONNECTOR_COLOR_FORMAT_YCBCR420: 2232 encoding = PIXEL_ENCODING_YCBCR420; 2233 break; 2234 default: 2235 encoding = PIXEL_ENCODING_UNDEFINED; 2236 break; 2237 } 2238 2239 return encoding == stream->timing.pixel_encoding ? 2240 DC_OK : DC_UNSUPPORTED_VALUE; 2241 } 2242 2243 struct dc_stream_state * 2244 amdgpu_dm_create_validate_stream_for_sink(struct drm_connector *connector, 2245 const struct drm_display_mode *drm_mode, 2246 const struct dm_connector_state *dm_state, 2247 const struct dc_stream_state *old_stream) 2248 { 2249 /* 2250 * Ordered lists of the encodings and bit depths we are willing to 2251 * validate, best quality/bandwidth first. The per-sink masks built 2252 * below gate which of these entries are actually attempted. 2253 */ 2254 static const enum dc_pixel_encoding encoding_order[] = { 2255 PIXEL_ENCODING_YCBCR444, 2256 PIXEL_ENCODING_RGB, 2257 PIXEL_ENCODING_YCBCR422, 2258 PIXEL_ENCODING_YCBCR420, 2259 }; 2260 static const u8 bpc_order[] = { 16, 12, 10, 8, 6 }; 2261 2262 struct amdgpu_dm_connector *aconnector = NULL; 2263 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2264 const struct drm_display_info *info = &connector->display_info; 2265 struct dc_stream_state *stream = NULL; 2266 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 2267 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 2268 enum dc_status dc_result = DC_OK; 2269 enum signal_type signal = SIGNAL_TYPE_NONE; 2270 bool want_420, want_422, is_dp_or_hdmi; 2271 u32 encoding_mask = 0; 2272 u32 bpc_mask = 0; 2273 bool is_hdmi_ep = false; 2274 unsigned int i, j; 2275 2276 if (!dm_state) 2277 return NULL; 2278 2279 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 2280 aconnector = to_amdgpu_dm_connector(connector); 2281 2282 /* 2283 * Writeback connectors have no sink EDID to enumerate against. They 2284 * only ever use RGB at the requested depth, so build and validate a 2285 * single stream directly and return it (dc_validate_stream() is not 2286 * meaningful for the writeback path). 2287 */ 2288 if (!aconnector) { 2289 stream = create_stream_for_sink(connector, drm_mode, dm_state, 2290 old_stream, requested_bpc, 2291 PIXEL_ENCODING_RGB, is_hdmi_ep); 2292 if (!stream) 2293 drm_err(adev_to_drm(adev), "Failed to create stream for sink!\n"); 2294 return stream; 2295 } 2296 2297 signal = aconnector->dc_link->connector_signal; 2298 2299 /* 2300 * Determine whether this is a native HDMI sink or a DP->HDMI dongle. 2301 * Since we check for it a few times below, cache the result. 2302 */ 2303 is_hdmi_ep = (signal == SIGNAL_TYPE_HDMI_TYPE_A || 2304 signal == SIGNAL_TYPE_HDMI_FRL || 2305 aconnector->dc_link->dpcd_caps.dongle_type == 2306 DISPLAY_DONGLE_DP_HDMI_CONVERTER); 2307 is_dp_or_hdmi = dc_is_hdmi_signal(signal) || dc_is_dp_signal(signal); 2308 2309 /* 2310 * Build the set of pixel encodings this sink advertises, so we only 2311 * ever validate combinations the display can actually accept. Ordered 2312 * best-first: RGB / YCbCr444 (full bandwidth) -> YCbCr422 -> YCbCr420. 2313 * 2314 * - RGB is the mandatory baseline and always available. 2315 * - YCbCr444 is only meaningful for native HDMI sinks. 2316 * - A 420-only mode collapses the mask to YCbCr420 alone. 2317 * - The debugfs force_yuv_pixel_format override pins the encoding to a 2318 * single dc_pixel_encoding when set (PIXEL_ENCODING_UNDEFINED means 2319 * "no override"). An explicit YCbCr420 force is honoured even on 2320 * modes the sink only lists as RGB/4:4:4 capable 2321 * (drm_mode_is_420_also() clear), as required for HDMI compliance 2322 * testing; dc_validate_stream() still rejects anything the link 2323 * genuinely cannot carry. The YCbCr422/YCbCr444 forces stay gated on 2324 * the sink's advertised caps. 2325 */ 2326 want_420 = (aconnector->force_yuv_pixel_format == PIXEL_ENCODING_YCBCR420) || 2327 (drm_state && drm_state->color_format == DRM_CONNECTOR_COLOR_FORMAT_YCBCR420); 2328 want_422 = (aconnector->force_yuv_pixel_format == PIXEL_ENCODING_YCBCR422) || 2329 (drm_state && drm_state->color_format == DRM_CONNECTOR_COLOR_FORMAT_YCBCR422); 2330 2331 if (drm_mode_is_420_only(info, drm_mode) && 2332 (want_420 || (drm_state && drm_state->color_format == DRM_CONNECTOR_COLOR_FORMAT_AUTO))) { 2333 encoding_mask = BIT(PIXEL_ENCODING_YCBCR420); 2334 } else if (drm_mode_is_420_also(info, drm_mode) && want_420) { 2335 encoding_mask = BIT(PIXEL_ENCODING_YCBCR420); 2336 } else if ((info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422)) && 2337 want_422 && is_dp_or_hdmi) { 2338 encoding_mask = BIT(PIXEL_ENCODING_YCBCR422); 2339 } else if (((aconnector->force_yuv_pixel_format == PIXEL_ENCODING_YCBCR444) || 2340 (drm_state && drm_state->color_format == DRM_CONNECTOR_COLOR_FORMAT_YCBCR444)) && 2341 (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444)) && 2342 is_dp_or_hdmi) { 2343 encoding_mask = BIT(PIXEL_ENCODING_YCBCR444); 2344 } else if (drm_state && drm_state->color_format == DRM_CONNECTOR_COLOR_FORMAT_RGB444) { 2345 encoding_mask = BIT(PIXEL_ENCODING_RGB); 2346 } else { 2347 encoding_mask = BIT(PIXEL_ENCODING_RGB); 2348 2349 if ((info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444)) && 2350 is_hdmi_ep) 2351 encoding_mask |= BIT(PIXEL_ENCODING_YCBCR444); 2352 2353 if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422)) 2354 encoding_mask |= BIT(PIXEL_ENCODING_YCBCR422); 2355 2356 if (drm_mode_is_420_also(info, drm_mode)) 2357 encoding_mask |= BIT(PIXEL_ENCODING_YCBCR420); 2358 } 2359 2360 /* 2361 * Build the set of bit depths to try, high-to-low. Start from the 2362 * atomic-requested cap and clear anything the sink cannot do: 2363 * 2364 * - Never exceed the requested bpc. 2365 * - HDMI/FRL and DP->HDMI dongles have no defined 6 bpc mode. 2366 * - Any depth above the EDID-reported bpc is dropped. 2367 * 2368 * amdgpu_dm_convert_color_depth_from_display_info() applies the final 2369 * per-encoding cap (e.g. YCbCr420 deep-colour limits) when the stream 2370 * is built, so this mask only needs the coarse sink limits. 2371 */ 2372 for (j = 0; j < ARRAY_SIZE(bpc_order); j++) { 2373 u8 bpc = bpc_order[j]; 2374 2375 if (requested_bpc > 0 && bpc > requested_bpc) 2376 continue; 2377 2378 if (bpc == 6 && is_hdmi_ep) 2379 continue; 2380 2381 if (info->bpc && bpc > info->bpc) 2382 continue; 2383 2384 bpc_mask |= BIT(bpc); 2385 } 2386 2387 /* 2388 * Enumerate the supported (encoding, bpc) combinations in priority 2389 * order and return the first that validates. Because the masks only 2390 * contain sink-supported entries, this is generic across connector 2391 * types and needs no encoding-specific fallback afterwards. 2392 * 2393 * The selection lives entirely on the stack and is passed by value to 2394 * create_stream_for_sink(); no shared connector state is mutated. This 2395 * matters because this helper runs concurrently from the connector 2396 * probe worker (->mode_valid) and from a compositor's atomic check on 2397 * the same connector. 2398 */ 2399 for (i = 0; i < ARRAY_SIZE(encoding_order); i++) { 2400 enum dc_pixel_encoding enc = encoding_order[i]; 2401 2402 if (!(encoding_mask & BIT(enc))) 2403 continue; 2404 2405 for (j = 0; j < ARRAY_SIZE(bpc_order); j++) { 2406 u8 bpc = bpc_order[j]; 2407 2408 if (!(bpc_mask & BIT(bpc))) 2409 continue; 2410 2411 drm_dbg_kms(connector->dev, 2412 "Trying %s with %d bpc (encoding_mask=0x%x bpc_mask=0x%x requested_bpc=%d drm max_bpc)\n", 2413 dc_pixel_encoding_to_str(enc), bpc, 2414 encoding_mask, bpc_mask, requested_bpc); 2415 2416 stream = create_stream_for_sink(connector, drm_mode, 2417 dm_state, old_stream, 2418 bpc, enc, is_hdmi_ep); 2419 if (stream == NULL) { 2420 drm_err(adev_to_drm(adev), "Failed to create stream for sink!\n"); 2421 return NULL; 2422 } 2423 2424 dc_result = dc_validate_stream(adev->dm.dc, stream); 2425 2426 if (dc_result == DC_OK && 2427 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2428 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 2429 2430 if (dc_result == DC_OK) 2431 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 2432 2433 if (dc_result == DC_OK) 2434 dc_result = dm_validate_stream_color_format(drm_state, stream); 2435 2436 if (dc_result == DC_OK) 2437 return stream; 2438 2439 drm_dbg_kms(connector->dev, "Pruned mode %d x %d (refresh rate %d) %s %s -- %s\n", 2440 drm_mode->hdisplay, 2441 drm_mode->vdisplay, 2442 drm_mode_vrefresh(drm_mode), 2443 dc_pixel_encoding_to_str(stream->timing.pixel_encoding), 2444 dc_color_depth_to_str(stream->timing.display_color_depth), 2445 dc_status_to_str(dc_result)); 2446 2447 dc_stream_release(stream); 2448 stream = NULL; 2449 } 2450 } 2451 2452 /* 2453 * Every sink-supported combination was exhausted without validating; 2454 * the mode is genuinely unsupported on this link. 2455 */ 2456 return NULL; 2457 } 2458 EXPORT_IF_KUNIT(amdgpu_dm_create_validate_stream_for_sink); 2459 2460 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 2461 const struct drm_display_mode *mode) 2462 { 2463 int result = MODE_ERROR; 2464 struct dc_sink *dc_sink; 2465 struct drm_display_mode *test_mode; 2466 /* TODO: Unhardcode stream count */ 2467 struct dc_stream_state *stream; 2468 /* we always have an amdgpu_dm_connector here since we got 2469 * here via the amdgpu_dm_connector_helper_funcs 2470 */ 2471 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2472 2473 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 2474 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 2475 return result; 2476 2477 /* 2478 * Only run this the first time mode_valid is called to initilialize 2479 * EDID mgmt 2480 */ 2481 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 2482 !aconnector->dc_em_sink) 2483 handle_edid_mgmt(aconnector); 2484 2485 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 2486 2487 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 2488 aconnector->base.force != DRM_FORCE_ON) { 2489 drm_err(connector->dev, "dc_sink is NULL!\n"); 2490 goto fail; 2491 } 2492 2493 test_mode = drm_mode_duplicate(connector->dev, mode); 2494 if (!test_mode) 2495 goto fail; 2496 2497 drm_mode_set_crtcinfo(test_mode, 0); 2498 2499 stream = amdgpu_dm_create_validate_stream_for_sink(connector, test_mode, 2500 to_dm_connector_state(connector->state), 2501 NULL); 2502 drm_mode_destroy(connector->dev, test_mode); 2503 if (stream) { 2504 dc_stream_release(stream); 2505 result = MODE_OK; 2506 } 2507 2508 fail: 2509 /* TODO: error handling*/ 2510 return result; 2511 } 2512 EXPORT_IF_KUNIT(amdgpu_dm_connector_mode_valid); 2513 2514 int amdgpu_dm_fill_hdr_info_packet(const struct drm_connector_state *state, 2515 struct dc_info_packet *out) 2516 { 2517 struct hdmi_drm_infoframe frame; 2518 unsigned char buf[30]; /* 26 + 4 */ 2519 ssize_t len; 2520 int ret, i; 2521 2522 memset(out, 0, sizeof(*out)); 2523 2524 if (!state->hdr_output_metadata) 2525 return 0; 2526 2527 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 2528 if (ret) 2529 return ret; 2530 2531 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 2532 if (len < 0) 2533 return (int)len; 2534 2535 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 2536 if (len != 30) 2537 return -EINVAL; 2538 2539 /* Prepare the infopacket for DC. */ 2540 switch (state->connector->connector_type) { 2541 case DRM_MODE_CONNECTOR_HDMIA: 2542 out->hb0 = 0x87; /* type */ 2543 out->hb1 = 0x01; /* version */ 2544 out->hb2 = 0x1A; /* length */ 2545 out->sb[0] = buf[3]; /* checksum */ 2546 i = 1; 2547 break; 2548 2549 case DRM_MODE_CONNECTOR_DisplayPort: 2550 case DRM_MODE_CONNECTOR_eDP: 2551 out->hb0 = 0x00; /* sdp id, zero */ 2552 out->hb1 = 0x87; /* type */ 2553 out->hb2 = 0x1D; /* payload len - 1 */ 2554 out->hb3 = (0x13 << 2); /* sdp version */ 2555 out->sb[0] = 0x01; /* version */ 2556 out->sb[1] = 0x1A; /* length */ 2557 i = 2; 2558 break; 2559 2560 default: 2561 return -EINVAL; 2562 } 2563 2564 memcpy(&out->sb[i], &buf[4], 26); 2565 out->valid = true; 2566 2567 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 2568 sizeof(out->sb), false); 2569 2570 return 0; 2571 } 2572 EXPORT_IF_KUNIT(amdgpu_dm_fill_hdr_info_packet); 2573 2574 static int 2575 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 2576 struct drm_atomic_commit *state) 2577 { 2578 struct drm_connector_state *new_con_state = 2579 drm_atomic_get_new_connector_state(state, conn); 2580 struct drm_connector_state *old_con_state = 2581 drm_atomic_get_old_connector_state(state, conn); 2582 struct drm_crtc *crtc; 2583 struct drm_crtc_state *new_crtc_state; 2584 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 2585 int ret; 2586 2587 if (WARN_ON(unlikely(!old_con_state || !new_con_state))) 2588 return -EINVAL; 2589 2590 trace_amdgpu_dm_connector_atomic_check(new_con_state); 2591 2592 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 2593 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 2594 if (ret < 0) 2595 return ret; 2596 } 2597 2598 crtc = new_con_state->crtc; 2599 if (!crtc) 2600 return 0; 2601 2602 if (new_con_state->privacy_screen_sw_state != old_con_state->privacy_screen_sw_state) { 2603 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 2604 if (IS_ERR(new_crtc_state)) 2605 return PTR_ERR(new_crtc_state); 2606 2607 new_crtc_state->mode_changed = true; 2608 } 2609 2610 if (new_con_state->colorspace != old_con_state->colorspace) { 2611 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 2612 if (IS_ERR(new_crtc_state)) 2613 return PTR_ERR(new_crtc_state); 2614 2615 new_crtc_state->mode_changed = true; 2616 } 2617 2618 if (new_con_state->content_type != old_con_state->content_type) { 2619 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 2620 if (IS_ERR(new_crtc_state)) 2621 return PTR_ERR(new_crtc_state); 2622 2623 new_crtc_state->mode_changed = true; 2624 } 2625 2626 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 2627 struct dc_info_packet hdr_infopacket; 2628 2629 ret = amdgpu_dm_fill_hdr_info_packet(new_con_state, &hdr_infopacket); 2630 if (ret) 2631 return ret; 2632 2633 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 2634 if (IS_ERR(new_crtc_state)) 2635 return PTR_ERR(new_crtc_state); 2636 2637 /* 2638 * DC considers the stream backends changed if the 2639 * static metadata changes. Forcing the modeset also 2640 * gives a simple way for userspace to switch from 2641 * 8bpc to 10bpc when setting the metadata to enter 2642 * or exit HDR. 2643 * 2644 * Changing the static metadata after it's been 2645 * set is permissible, however. So only force a 2646 * modeset if we're entering or exiting HDR. 2647 */ 2648 new_crtc_state->mode_changed = new_crtc_state->mode_changed || 2649 !old_con_state->hdr_output_metadata || 2650 !new_con_state->hdr_output_metadata; 2651 } 2652 2653 return 0; 2654 } 2655 2656 static const struct drm_connector_helper_funcs 2657 amdgpu_dm_connector_helper_funcs = { 2658 /* 2659 * If hotplugging a second bigger display in FB Con mode, bigger resolution 2660 * modes will be filtered by drm_mode_validate_size(), and those modes 2661 * are missing after user start lightdm. So we need to renew modes list. 2662 * in get_modes call back, not just return the modes count 2663 */ 2664 .get_modes = get_modes, 2665 .mode_valid = amdgpu_dm_connector_mode_valid, 2666 .atomic_check = amdgpu_dm_connector_atomic_check, 2667 }; 2668 2669 int amdgpu_dm_convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 2670 { 2671 switch (display_color_depth) { 2672 case COLOR_DEPTH_666: 2673 return 6; 2674 case COLOR_DEPTH_888: 2675 return 8; 2676 case COLOR_DEPTH_101010: 2677 return 10; 2678 case COLOR_DEPTH_121212: 2679 return 12; 2680 case COLOR_DEPTH_141414: 2681 return 14; 2682 case COLOR_DEPTH_161616: 2683 return 16; 2684 default: 2685 break; 2686 } 2687 return 0; 2688 } 2689 EXPORT_IF_KUNIT(amdgpu_dm_convert_dc_color_depth_into_bpc); 2690 2691 STATIC_IFN_KUNIT int to_drm_connector_type(enum signal_type st, uint32_t connector_id) 2692 { 2693 switch (st) { 2694 case SIGNAL_TYPE_HDMI_TYPE_A: 2695 return DRM_MODE_CONNECTOR_HDMIA; 2696 case SIGNAL_TYPE_EDP: 2697 return DRM_MODE_CONNECTOR_eDP; 2698 case SIGNAL_TYPE_LVDS: 2699 return DRM_MODE_CONNECTOR_LVDS; 2700 case SIGNAL_TYPE_RGB: 2701 return DRM_MODE_CONNECTOR_VGA; 2702 case SIGNAL_TYPE_DISPLAY_PORT: 2703 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2704 /* External DP bridges have a different connector type. */ 2705 if (connector_id == CONNECTOR_ID_VGA) 2706 return DRM_MODE_CONNECTOR_VGA; 2707 else if (connector_id == CONNECTOR_ID_LVDS) 2708 return DRM_MODE_CONNECTOR_LVDS; 2709 2710 return DRM_MODE_CONNECTOR_DisplayPort; 2711 case SIGNAL_TYPE_DVI_DUAL_LINK: 2712 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2713 if (connector_id == CONNECTOR_ID_SINGLE_LINK_DVII || 2714 connector_id == CONNECTOR_ID_DUAL_LINK_DVII) 2715 return DRM_MODE_CONNECTOR_DVII; 2716 2717 return DRM_MODE_CONNECTOR_DVID; 2718 case SIGNAL_TYPE_VIRTUAL: 2719 return DRM_MODE_CONNECTOR_VIRTUAL; 2720 2721 default: 2722 return DRM_MODE_CONNECTOR_Unknown; 2723 } 2724 } 2725 EXPORT_IF_KUNIT(to_drm_connector_type); 2726 2727 STATIC_IFN_KUNIT struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 2728 { 2729 struct drm_encoder *encoder; 2730 2731 /* There is only one encoder per connector */ 2732 drm_connector_for_each_possible_encoder(connector, encoder) 2733 return encoder; 2734 2735 return NULL; 2736 } 2737 EXPORT_IF_KUNIT(amdgpu_dm_connector_to_encoder); 2738 2739 STATIC_IFN_KUNIT void amdgpu_dm_get_native_mode(struct drm_connector *connector) 2740 { 2741 struct drm_encoder *encoder; 2742 struct amdgpu_encoder *amdgpu_encoder; 2743 2744 encoder = amdgpu_dm_connector_to_encoder(connector); 2745 2746 if (encoder == NULL) 2747 return; 2748 2749 amdgpu_encoder = to_amdgpu_encoder(encoder); 2750 2751 amdgpu_encoder->native_mode.clock = 0; 2752 2753 if (!list_empty(&connector->probed_modes)) { 2754 struct drm_display_mode *preferred_mode = NULL; 2755 2756 list_for_each_entry(preferred_mode, 2757 &connector->probed_modes, 2758 head) { 2759 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 2760 amdgpu_encoder->native_mode = *preferred_mode; 2761 2762 break; 2763 } 2764 2765 } 2766 } 2767 EXPORT_IF_KUNIT(amdgpu_dm_get_native_mode); 2768 2769 STATIC_IFN_KUNIT struct drm_display_mode * 2770 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 2771 const char *name, 2772 int hdisplay, int vdisplay) 2773 { 2774 struct drm_device *dev = encoder->dev; 2775 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2776 struct drm_display_mode *mode = NULL; 2777 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 2778 2779 mode = drm_mode_duplicate(dev, native_mode); 2780 2781 if (mode == NULL) 2782 return NULL; 2783 2784 mode->hdisplay = hdisplay; 2785 mode->vdisplay = vdisplay; 2786 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2787 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 2788 2789 return mode; 2790 2791 } 2792 EXPORT_IF_KUNIT(amdgpu_dm_create_common_mode); 2793 2794 static const struct amdgpu_dm_mode_size { 2795 char name[DRM_DISPLAY_MODE_LEN]; 2796 int w; 2797 int h; 2798 } common_modes[] = { 2799 { "640x480", 640, 480}, 2800 { "800x600", 800, 600}, 2801 { "1024x768", 1024, 768}, 2802 { "1280x720", 1280, 720}, 2803 { "1280x800", 1280, 800}, 2804 {"1280x1024", 1280, 1024}, 2805 { "1440x900", 1440, 900}, 2806 {"1680x1050", 1680, 1050}, 2807 {"1600x1200", 1600, 1200}, 2808 {"1920x1080", 1920, 1080}, 2809 {"1920x1200", 1920, 1200} 2810 }; 2811 2812 STATIC_IFN_KUNIT void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 2813 struct drm_connector *connector) 2814 { 2815 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2816 struct drm_display_mode *mode = NULL; 2817 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 2818 struct amdgpu_dm_connector *amdgpu_dm_connector = 2819 to_amdgpu_dm_connector(connector); 2820 int i; 2821 int n; 2822 2823 if ((connector->connector_type != DRM_MODE_CONNECTOR_eDP) && 2824 (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) 2825 return; 2826 2827 n = ARRAY_SIZE(common_modes); 2828 2829 for (i = 0; i < n; i++) { 2830 struct drm_display_mode *curmode = NULL; 2831 bool mode_existed = false; 2832 2833 if (common_modes[i].w > native_mode->hdisplay || 2834 common_modes[i].h > native_mode->vdisplay || 2835 (common_modes[i].w == native_mode->hdisplay && 2836 common_modes[i].h == native_mode->vdisplay)) 2837 continue; 2838 2839 list_for_each_entry(curmode, &connector->probed_modes, head) { 2840 if (common_modes[i].w == curmode->hdisplay && 2841 common_modes[i].h == curmode->vdisplay) { 2842 mode_existed = true; 2843 break; 2844 } 2845 } 2846 2847 if (mode_existed) 2848 continue; 2849 2850 mode = amdgpu_dm_create_common_mode(encoder, 2851 common_modes[i].name, common_modes[i].w, 2852 common_modes[i].h); 2853 if (!mode) 2854 continue; 2855 2856 drm_mode_probed_add(connector, mode); 2857 amdgpu_dm_connector->num_modes++; 2858 } 2859 } 2860 EXPORT_IF_KUNIT(amdgpu_dm_connector_add_common_modes); 2861 2862 void amdgpu_set_panel_orientation(struct drm_connector *connector) 2863 { 2864 struct drm_encoder *encoder; 2865 struct amdgpu_encoder *amdgpu_encoder; 2866 const struct drm_display_mode *native_mode; 2867 2868 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 2869 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 2870 return; 2871 2872 mutex_lock(&connector->dev->mode_config.mutex); 2873 amdgpu_dm_connector_get_modes(connector); 2874 mutex_unlock(&connector->dev->mode_config.mutex); 2875 2876 encoder = amdgpu_dm_connector_to_encoder(connector); 2877 if (!encoder) 2878 return; 2879 2880 amdgpu_encoder = to_amdgpu_encoder(encoder); 2881 2882 native_mode = &amdgpu_encoder->native_mode; 2883 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 2884 return; 2885 2886 drm_connector_set_panel_orientation_with_quirk(connector, 2887 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 2888 native_mode->hdisplay, 2889 native_mode->vdisplay); 2890 } 2891 2892 /* 2893 * The Apple Studio Display primary tile advertises both the full 5120x2880 2894 * mode and the per-tile 2560x2880 timing. As the secondary tile is hidden from 2895 * userspace (see amdgpu_dm_hide_secondary_tile_from_userspace()), drop the 2896 * per-tile timing from the primary connector so compositors only pick the full 2897 * 5K mode. 2898 */ 2899 static void amdgpu_dm_prune_primary_tile_modes(struct drm_connector *connector) 2900 { 2901 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2902 struct drm_display_mode *mode, *t; 2903 2904 if (!aconnector->dc_sink) 2905 return; 2906 2907 if (!aconnector->dc_sink->edid_caps.panel_patch.disable_second_tile) 2908 return; 2909 2910 if (!connector->has_tile) 2911 return; 2912 2913 /* Only prune the per-tile timing from the primary tile. */ 2914 if (connector->tile_h_loc || connector->tile_v_loc) 2915 return; 2916 2917 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 2918 if (mode->hdisplay != connector->tile_h_size || 2919 mode->vdisplay != connector->tile_v_size) 2920 continue; 2921 2922 drm_dbg_kms(connector->dev, 2923 "[CONNECTOR:%d:%s] pruning per-tile %dx%d timing from primary Apple Studio Display tile\n", 2924 connector->base.id, connector->name, 2925 mode->hdisplay, mode->vdisplay); 2926 2927 list_del(&mode->head); 2928 drm_mode_destroy(connector->dev, mode); 2929 aconnector->num_modes--; 2930 } 2931 } 2932 2933 STATIC_IFN_KUNIT void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 2934 const struct drm_edid *drm_edid) 2935 { 2936 struct amdgpu_dm_connector *amdgpu_dm_connector = 2937 to_amdgpu_dm_connector(connector); 2938 2939 if (drm_edid) { 2940 /* empty probed_modes */ 2941 INIT_LIST_HEAD(&connector->probed_modes); 2942 amdgpu_dm_connector->num_modes = 2943 drm_edid_connector_add_modes(connector); 2944 2945 amdgpu_dm_prune_primary_tile_modes(connector); 2946 2947 /* sorting the probed modes before calling function 2948 * amdgpu_dm_get_native_mode() since EDID can have 2949 * more than one preferred mode. The modes that are 2950 * later in the probed mode list could be of higher 2951 * and preferred resolution. For example, 3840x2160 2952 * resolution in base EDID preferred timing and 4096x2160 2953 * preferred resolution in DID extension block later. 2954 */ 2955 drm_mode_sort(&connector->probed_modes); 2956 amdgpu_dm_get_native_mode(connector); 2957 2958 /* Freesync capabilities are reset by calling 2959 * drm_edid_connector_add_modes() and need to be 2960 * restored here. 2961 */ 2962 amdgpu_dm_update_freesync_caps(connector, drm_edid, false); 2963 } else { 2964 amdgpu_dm_connector->num_modes = 0; 2965 } 2966 } 2967 EXPORT_IF_KUNIT(amdgpu_dm_connector_ddc_get_modes); 2968 2969 STATIC_IFN_KUNIT bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 2970 struct drm_display_mode *mode) 2971 { 2972 struct drm_display_mode *m; 2973 2974 list_for_each_entry(m, &aconnector->base.probed_modes, head) { 2975 if (drm_mode_equal(m, mode)) 2976 return true; 2977 } 2978 2979 return false; 2980 } 2981 EXPORT_IF_KUNIT(is_duplicate_mode); 2982 2983 STATIC_IFN_KUNIT uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 2984 { 2985 const struct drm_display_mode *m; 2986 struct drm_display_mode *new_mode; 2987 uint i; 2988 u32 new_modes_count = 0; 2989 2990 /* Standard FPS values 2991 * 2992 * 23.976 - TV/NTSC 2993 * 24 - Cinema 2994 * 25 - TV/PAL 2995 * 29.97 - TV/NTSC 2996 * 30 - TV/NTSC 2997 * 48 - Cinema HFR 2998 * 50 - TV/PAL 2999 * 60 - Commonly used 3000 * 48,72,96,120 - Multiples of 24 3001 */ 3002 static const u32 common_rates[] = { 3003 23976, 24000, 25000, 29970, 30000, 3004 48000, 50000, 60000, 72000, 96000, 120000 3005 }; 3006 3007 /* 3008 * Find mode with highest refresh rate with the same resolution 3009 * as the preferred mode. Some monitors report a preferred mode 3010 * with lower resolution than the highest refresh rate supported. 3011 */ 3012 3013 m = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, true); 3014 if (!m) 3015 return 0; 3016 3017 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 3018 u64 target_vtotal, target_vtotal_diff; 3019 u64 num, den; 3020 3021 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 3022 continue; 3023 3024 if (common_rates[i] < aconnector->min_vfreq * 1000 || 3025 common_rates[i] > aconnector->max_vfreq * 1000) 3026 continue; 3027 3028 num = (unsigned long long)m->clock * 1000 * 1000; 3029 den = common_rates[i] * (unsigned long long)m->htotal; 3030 target_vtotal = div_u64(num, den); 3031 target_vtotal_diff = target_vtotal - m->vtotal; 3032 3033 /* Check for illegal modes */ 3034 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 3035 m->vsync_end + target_vtotal_diff < m->vsync_start || 3036 m->vtotal + target_vtotal_diff < m->vsync_end) 3037 continue; 3038 3039 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 3040 if (!new_mode) 3041 goto out; 3042 3043 new_mode->vtotal += (u16)target_vtotal_diff; 3044 new_mode->vsync_start += (u16)target_vtotal_diff; 3045 new_mode->vsync_end += (u16)target_vtotal_diff; 3046 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 3047 new_mode->type |= DRM_MODE_TYPE_DRIVER; 3048 3049 if (!is_duplicate_mode(aconnector, new_mode)) { 3050 drm_mode_probed_add(&aconnector->base, new_mode); 3051 new_modes_count += 1; 3052 } else 3053 drm_mode_destroy(aconnector->base.dev, new_mode); 3054 } 3055 out: 3056 return new_modes_count; 3057 } 3058 EXPORT_IF_KUNIT(add_fs_modes); 3059 3060 STATIC_IFN_KUNIT void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 3061 const struct drm_edid *drm_edid) 3062 { 3063 struct amdgpu_dm_connector *amdgpu_dm_connector = 3064 to_amdgpu_dm_connector(connector); 3065 3066 if (!(amdgpu_freesync_vid_mode && drm_edid)) 3067 return; 3068 3069 if (!amdgpu_dm_connector->dc_sink || !amdgpu_dm_connector->dc_link) 3070 return; 3071 3072 if (!dc_supports_vrr(amdgpu_dm_connector->dc_sink->ctx->dce_version)) 3073 return; 3074 3075 if (dc_connector_supports_analog(amdgpu_dm_connector->dc_link->link_id.id) && 3076 amdgpu_dm_connector->dc_sink->edid_caps.analog) 3077 return; 3078 3079 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 3080 amdgpu_dm_connector->num_modes += 3081 add_fs_modes(amdgpu_dm_connector); 3082 } 3083 EXPORT_IF_KUNIT(amdgpu_dm_connector_add_freesync_modes); 3084 3085 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 3086 { 3087 struct amdgpu_dm_connector *amdgpu_dm_connector = 3088 to_amdgpu_dm_connector(connector); 3089 struct dc_link *dc_link = amdgpu_dm_connector->dc_link; 3090 struct drm_encoder *encoder; 3091 const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid; 3092 struct dc_link_settings *verified_link_cap = &dc_link->verified_link_cap; 3093 const struct dc *dc = dc_link->dc; 3094 3095 encoder = amdgpu_dm_connector_to_encoder(connector); 3096 3097 if (!drm_edid) { 3098 amdgpu_dm_connector->num_modes = 3099 drm_add_modes_noedid(connector, 640, 480); 3100 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 3101 amdgpu_dm_connector->num_modes += 3102 drm_add_modes_noedid(connector, 1920, 1080); 3103 3104 if (amdgpu_dm_connector->dc_sink && 3105 amdgpu_dm_connector->dc_sink->edid_caps.analog && 3106 dc_connector_supports_analog(dc_link->link_id.id)) { 3107 /* Analog monitor connected by DAC load detection. 3108 * Add common modes. It will be up to the user to select one that works. 3109 */ 3110 for (int i = 0; i < ARRAY_SIZE(common_modes); i++) 3111 amdgpu_dm_connector->num_modes += drm_add_modes_noedid( 3112 connector, common_modes[i].w, common_modes[i].h); 3113 } 3114 } else { 3115 amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); 3116 if (encoder) 3117 amdgpu_dm_connector_add_common_modes(encoder, connector); 3118 amdgpu_dm_connector_add_freesync_modes(connector, drm_edid); 3119 } 3120 amdgpu_dm_fbc_init(connector); 3121 3122 return amdgpu_dm_connector->num_modes; 3123 } 3124 3125 static const u32 supported_colorspaces = 3126 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | 3127 BIT(DRM_MODE_COLORIMETRY_OPRGB) | 3128 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | 3129 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); 3130 3131 static const u32 supported_colorformats = 3132 BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444) | 3133 BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444) | 3134 BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422) | 3135 BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR420); 3136 3137 static void hdmi_frl_status_polling_work(struct work_struct *work) 3138 { 3139 struct amdgpu_display_manager *dm = 3140 container_of(to_delayed_work(work), struct amdgpu_display_manager, 3141 hdmi_frl_status_polling_work); 3142 struct dc *dc = dm->dc; 3143 struct dc_link *dc_link; 3144 bool link_update = false; 3145 3146 for (int i = 0; i < MAX_LINKS; i++) { 3147 dc_link = dc->links[i]; 3148 3149 3150 if (!dc_link || !dc_link->local_sink) 3151 continue; 3152 3153 if (!dc_is_hdmi_signal(dc_link->connector_signal)) 3154 continue; 3155 3156 if (dc_link->frl_link_settings.frl_link_rate == 0) 3157 continue; 3158 3159 link_update = dc_link_frl_poll_status_flag(dc_link); 3160 if (link_update) { 3161 mutex_lock(&dm->dc_lock); 3162 dc_link_detect(dc_link, DETECT_REASON_RETRAIN); 3163 mutex_unlock(&dm->dc_lock); 3164 } 3165 } 3166 3167 queue_delayed_work(dm->hdmi_frl_status_polling_wq, 3168 &dm->hdmi_frl_status_polling_work, 3169 msecs_to_jiffies(dm->hdmi_frl_status_polling_delay_ms)); 3170 } 3171 3172 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 3173 struct amdgpu_dm_connector *aconnector, 3174 int connector_type, 3175 struct dc_link *link, 3176 int link_index) 3177 { 3178 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 3179 3180 /* 3181 * Some of the properties below require access to state, like bpc. 3182 * Allocate some default initial connector state with our reset helper. 3183 */ 3184 if (aconnector->base.funcs->reset) 3185 aconnector->base.funcs->reset(&aconnector->base); 3186 3187 aconnector->connector_id = link_index; 3188 aconnector->bl_idx = -1; 3189 aconnector->dc_link = link; 3190 aconnector->base.interlace_allowed = false; 3191 aconnector->base.doublescan_allowed = false; 3192 aconnector->base.stereo_allowed = false; 3193 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 3194 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 3195 aconnector->audio_inst = -1; 3196 aconnector->pack_sdp_v1_3 = false; 3197 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 3198 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 3199 mutex_init(&aconnector->hpd_lock); 3200 mutex_init(&aconnector->handle_mst_msg_ready); 3201 3202 /* 3203 * If HDMI HPD debounce delay is set, use the minimum between selected 3204 * value and AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 3205 */ 3206 if (amdgpu_hdmi_hpd_debounce_delay_ms) { 3207 aconnector->hdmi_hpd_debounce_delay_ms = min(amdgpu_hdmi_hpd_debounce_delay_ms, 3208 AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS); 3209 INIT_DELAYED_WORK(&aconnector->hdmi_hpd_debounce_work, amdgpu_dm_hdmi_hpd_debounce_work); 3210 aconnector->hdmi_prev_sink = NULL; 3211 } else { 3212 aconnector->hdmi_hpd_debounce_delay_ms = 0; 3213 } 3214 3215 dm->hdmi_frl_status_polling_delay_ms = 200; 3216 INIT_DELAYED_WORK(&dm->hdmi_frl_status_polling_work, hdmi_frl_status_polling_work); 3217 /* 3218 * configure support HPD hot plug connector_>polled default value is 0 3219 * which means HPD hot plug not supported 3220 */ 3221 switch (connector_type) { 3222 case DRM_MODE_CONNECTOR_HDMIA: 3223 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3224 aconnector->base.ycbcr_420_allowed = 3225 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 3226 break; 3227 case DRM_MODE_CONNECTOR_DisplayPort: 3228 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3229 link->link_enc = link_enc_cfg_get_link_enc(link); 3230 ASSERT(link->link_enc); 3231 if (link->link_enc) 3232 aconnector->base.ycbcr_420_allowed = 3233 link->link_enc->features.dp_ycbcr420_supported ? true : false; 3234 break; 3235 case DRM_MODE_CONNECTOR_DVID: 3236 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3237 break; 3238 case DRM_MODE_CONNECTOR_DVII: 3239 case DRM_MODE_CONNECTOR_VGA: 3240 aconnector->base.polled = 3241 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 3242 break; 3243 default: 3244 break; 3245 } 3246 3247 drm_object_attach_property(&aconnector->base.base, 3248 dm->ddev->mode_config.scaling_mode_property, 3249 DRM_MODE_SCALE_NONE); 3250 3251 if (connector_type == DRM_MODE_CONNECTOR_HDMIA 3252 || (connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root)) 3253 drm_connector_attach_broadcast_rgb_property(&aconnector->base); 3254 3255 drm_object_attach_property(&aconnector->base.base, 3256 adev->mode_info.underscan_property, 3257 UNDERSCAN_OFF); 3258 drm_object_attach_property(&aconnector->base.base, 3259 adev->mode_info.underscan_hborder_property, 3260 0); 3261 drm_object_attach_property(&aconnector->base.base, 3262 adev->mode_info.underscan_vborder_property, 3263 0); 3264 3265 if (!aconnector->mst_root) 3266 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 3267 3268 aconnector->base.state->max_bpc = 16; 3269 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 3270 3271 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3272 /* Content Type is currently only implemented for HDMI. */ 3273 drm_connector_attach_content_type_property(&aconnector->base); 3274 } 3275 3276 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3277 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) 3278 drm_connector_attach_colorspace_property(&aconnector->base); 3279 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || 3280 connector_type == DRM_MODE_CONNECTOR_eDP) { 3281 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) 3282 drm_connector_attach_colorspace_property(&aconnector->base); 3283 } 3284 3285 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 3286 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3287 connector_type == DRM_MODE_CONNECTOR_eDP) { 3288 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 3289 3290 if (!aconnector->mst_root) { 3291 drm_connector_attach_vrr_capable_property(&aconnector->base); 3292 drm_connector_attach_color_format_property(&aconnector->base, 3293 supported_colorformats); 3294 } 3295 3296 3297 if (adev->dm.hdcp_workqueue) 3298 drm_connector_attach_content_protection_property(&aconnector->base, true); 3299 } 3300 3301 if (connector_type == DRM_MODE_CONNECTOR_eDP) { 3302 struct drm_privacy_screen *privacy_screen; 3303 3304 drm_connector_attach_panel_type_property(&aconnector->base); 3305 3306 privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)->dev, NULL); 3307 if (!IS_ERR(privacy_screen)) { 3308 drm_connector_attach_privacy_screen_provider(&aconnector->base, 3309 privacy_screen); 3310 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3311 drm_warn(adev_to_drm(adev), "Error getting privacy-screen\n"); 3312 } 3313 } 3314 } 3315 3316 STATIC_IFN_KUNIT int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 3317 struct i2c_msg *msgs, int num) 3318 { 3319 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 3320 struct ddc_service *ddc_service = i2c->ddc_service; 3321 struct i2c_command cmd; 3322 int i; 3323 int result = -EIO; 3324 3325 if (!ddc_service->ddc_pin) 3326 return result; 3327 3328 cmd.payloads = kzalloc_objs(struct i2c_payload, num); 3329 3330 if (!cmd.payloads) 3331 return result; 3332 3333 cmd.number_of_payloads = num; 3334 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 3335 cmd.speed = 100; 3336 3337 for (i = 0; i < num; i++) { 3338 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 3339 cmd.payloads[i].address = msgs[i].addr; 3340 cmd.payloads[i].length = msgs[i].len; 3341 cmd.payloads[i].data = msgs[i].buf; 3342 } 3343 3344 if (i2c->oem) { 3345 if (dc_submit_i2c_oem( 3346 ddc_service->ctx->dc, 3347 &cmd)) 3348 result = num; 3349 } else { 3350 if (dc_submit_i2c( 3351 ddc_service->ctx->dc, 3352 ddc_service->link->link_index, 3353 &cmd)) 3354 result = num; 3355 } 3356 3357 kfree(cmd.payloads); 3358 return result; 3359 } 3360 EXPORT_IF_KUNIT(amdgpu_dm_i2c_xfer); 3361 3362 STATIC_IFN_KUNIT u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 3363 { 3364 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3365 } 3366 EXPORT_IF_KUNIT(amdgpu_dm_i2c_func); 3367 3368 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 3369 .master_xfer = amdgpu_dm_i2c_xfer, 3370 .functionality = amdgpu_dm_i2c_func, 3371 }; 3372 3373 struct amdgpu_i2c_adapter * 3374 amdgpu_dm_create_i2c(struct ddc_service *ddc_service, bool oem) 3375 { 3376 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 3377 struct amdgpu_i2c_adapter *i2c; 3378 3379 i2c = kzalloc_obj(struct amdgpu_i2c_adapter); 3380 if (!i2c) 3381 return NULL; 3382 i2c->base.owner = THIS_MODULE; 3383 i2c->base.dev.parent = &adev->pdev->dev; 3384 i2c->base.algo = &amdgpu_dm_i2c_algo; 3385 if (oem) 3386 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c OEM bus"); 3387 else 3388 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", 3389 ddc_service->link->link_index); 3390 i2c_set_adapdata(&i2c->base, i2c); 3391 i2c->ddc_service = ddc_service; 3392 i2c->oem = oem; 3393 3394 return i2c; 3395 } 3396 3397 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector) 3398 { 3399 struct cec_connector_info conn_info; 3400 struct drm_device *ddev = aconnector->base.dev; 3401 struct device *hdmi_dev = ddev->dev; 3402 3403 if (amdgpu_dc_debug_mask & DC_DISABLE_HDMI_CEC) { 3404 drm_info(ddev, "HDMI-CEC feature masked\n"); 3405 return -EINVAL; 3406 } 3407 3408 cec_fill_conn_info_from_drm(&conn_info, &aconnector->base); 3409 aconnector->notifier = 3410 cec_notifier_conn_register(hdmi_dev, NULL, &conn_info); 3411 if (!aconnector->notifier) { 3412 drm_err(ddev, "Failed to create cec notifier\n"); 3413 return -ENOMEM; 3414 } 3415 3416 return 0; 3417 } 3418 3419 /* 3420 * Note: this function assumes that dc_link_detect() was called for the 3421 * dc_link which will be represented by this aconnector. 3422 */ 3423 int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 3424 struct amdgpu_dm_connector *aconnector, 3425 u32 link_index, 3426 struct amdgpu_encoder *aencoder) 3427 { 3428 int res = 0; 3429 int connector_type; 3430 struct dc *dc = dm->dc; 3431 struct dc_link *link = dc_get_link_at_index(dc, link_index); 3432 struct amdgpu_i2c_adapter *i2c; 3433 3434 /* Not needed for writeback connector */ 3435 link->priv = aconnector; 3436 3437 3438 i2c = amdgpu_dm_create_i2c(link->ddc, false); 3439 if (!i2c) { 3440 drm_err(adev_to_drm(dm->adev), "Failed to create i2c adapter data\n"); 3441 return -ENOMEM; 3442 } 3443 3444 aconnector->i2c = i2c; 3445 res = devm_i2c_add_adapter(dm->adev->dev, &i2c->base); 3446 3447 if (res) { 3448 drm_err(adev_to_drm(dm->adev), "Failed to register hw i2c %d\n", link->link_index); 3449 goto out_free; 3450 } 3451 3452 connector_type = to_drm_connector_type(link->connector_signal, link->link_id.id); 3453 3454 res = drm_connector_init_with_ddc( 3455 dm->ddev, 3456 &aconnector->base, 3457 &amdgpu_dm_connector_funcs, 3458 connector_type, 3459 &i2c->base); 3460 3461 if (res) { 3462 drm_err(adev_to_drm(dm->adev), "connector_init failed\n"); 3463 aconnector->connector_id = -1; 3464 goto out_free; 3465 } 3466 3467 drm_connector_helper_add( 3468 &aconnector->base, 3469 &amdgpu_dm_connector_helper_funcs); 3470 3471 amdgpu_dm_connector_init_helper( 3472 dm, 3473 aconnector, 3474 connector_type, 3475 link, 3476 link_index); 3477 3478 drm_connector_attach_encoder( 3479 &aconnector->base, &aencoder->base); 3480 3481 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 3482 connector_type == DRM_MODE_CONNECTOR_HDMIB) 3483 amdgpu_dm_initialize_hdmi_connector(aconnector); 3484 3485 if (dc_is_dp_signal(link->connector_signal)) 3486 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 3487 3488 out_free: 3489 if (res) { 3490 kfree(i2c); 3491 aconnector->i2c = NULL; 3492 } 3493 return res; 3494 } 3495 3496 static int dm_force_atomic_commit(struct drm_connector *connector) 3497 { 3498 int ret = 0; 3499 struct drm_device *ddev = connector->dev; 3500 struct drm_atomic_commit *state = drm_atomic_commit_alloc(ddev); 3501 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 3502 struct drm_plane *plane = disconnected_acrtc->base.primary; 3503 struct drm_connector_state *conn_state; 3504 struct drm_crtc_state *crtc_state; 3505 struct drm_plane_state *plane_state; 3506 3507 if (!state) 3508 return -ENOMEM; 3509 3510 state->acquire_ctx = ddev->mode_config.acquire_ctx; 3511 3512 /* Construct an atomic state to restore previous display setting */ 3513 3514 /* 3515 * Attach connectors to drm_atomic_commit 3516 */ 3517 conn_state = drm_atomic_get_connector_state(state, connector); 3518 3519 /* Check for error in getting connector state */ 3520 if (IS_ERR(conn_state)) { 3521 ret = PTR_ERR(conn_state); 3522 goto out; 3523 } 3524 3525 /* Attach crtc to drm_atomic_commit*/ 3526 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 3527 3528 /* Check for error in getting crtc state */ 3529 if (IS_ERR(crtc_state)) { 3530 ret = PTR_ERR(crtc_state); 3531 goto out; 3532 } 3533 3534 /* force a restore */ 3535 crtc_state->mode_changed = true; 3536 3537 /* Attach plane to drm_atomic_commit */ 3538 plane_state = drm_atomic_get_plane_state(state, plane); 3539 3540 /* Check for error in getting plane state */ 3541 if (IS_ERR(plane_state)) { 3542 ret = PTR_ERR(plane_state); 3543 goto out; 3544 } 3545 3546 /* Call commit internally with the state we just constructed */ 3547 ret = drm_atomic_commit(state); 3548 3549 out: 3550 drm_atomic_commit_put(state); 3551 if (ret) 3552 drm_err(ddev, "Restoring old state failed with %i\n", ret); 3553 3554 return ret; 3555 } 3556 3557 /* 3558 * This function handles all cases when set mode does not come upon hotplug. 3559 * This includes when a display is unplugged then plugged back into the 3560 * same port and when running without usermode desktop manager support 3561 */ 3562 void dm_restore_drm_connector_state(struct drm_device *dev, 3563 struct drm_connector *connector) 3564 { 3565 struct amdgpu_dm_connector *aconnector; 3566 struct amdgpu_crtc *disconnected_acrtc; 3567 struct dm_crtc_state *acrtc_state; 3568 3569 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3570 return; 3571 3572 aconnector = to_amdgpu_dm_connector(connector); 3573 3574 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 3575 return; 3576 3577 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 3578 if (!disconnected_acrtc) 3579 return; 3580 3581 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 3582 if (!acrtc_state->stream) 3583 return; 3584 3585 /* 3586 * If the previous sink is not released and different from the current, 3587 * we deduce we are in a state where we can not rely on usermode call 3588 * to turn on the display, so we do it here 3589 */ 3590 if (acrtc_state->stream->sink != aconnector->dc_sink) 3591 dm_force_atomic_commit(&aconnector->base); 3592 } 3593 3594 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 3595 unsigned int offset, 3596 unsigned int total_length, 3597 u8 *data, 3598 unsigned int length, 3599 struct amdgpu_hdmi_vsdb_info *vsdb) 3600 { 3601 bool res; 3602 union dmub_rb_cmd cmd; 3603 struct dmub_cmd_send_edid_cea *input; 3604 struct dmub_cmd_edid_cea_output *output; 3605 3606 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 3607 return false; 3608 3609 memset(&cmd, 0, sizeof(cmd)); 3610 3611 input = &cmd.edid_cea.data.input; 3612 3613 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 3614 cmd.edid_cea.header.sub_type = 0; 3615 cmd.edid_cea.header.payload_bytes = 3616 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 3617 input->offset = offset; 3618 input->length = length; 3619 input->cea_total_length = total_length; 3620 memcpy(input->payload, data, length); 3621 3622 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); 3623 if (!res) { 3624 drm_err(adev_to_drm(dm->adev), "EDID CEA parser failed\n"); 3625 return false; 3626 } 3627 3628 output = &cmd.edid_cea.data.output; 3629 3630 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 3631 if (!output->ack.success) { 3632 drm_err(adev_to_drm(dm->adev), "EDID CEA ack failed at offset %d\n", 3633 output->ack.offset); 3634 } 3635 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 3636 if (!output->amd_vsdb.vsdb_found) 3637 return false; 3638 3639 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 3640 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 3641 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 3642 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 3643 vsdb->freesync_mccs_vcp_code = output->amd_vsdb.freesync_mccs_vcp_code; 3644 } else { 3645 drm_warn(adev_to_drm(dm->adev), "Unknown EDID CEA parser results\n"); 3646 return false; 3647 } 3648 3649 return true; 3650 } 3651 3652 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 3653 u8 *edid_ext, int len, 3654 struct amdgpu_hdmi_vsdb_info *vsdb_info) 3655 { 3656 int i; 3657 3658 /* send extension block to DMCU for parsing */ 3659 for (i = 0; i < len; i += 8) { 3660 bool res; 3661 int offset; 3662 3663 /* send 8 bytes a time */ 3664 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 3665 return false; 3666 3667 if (i+8 == len) { 3668 /* EDID block sent completed, expect result */ 3669 int version, min_rate, max_rate; 3670 3671 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 3672 if (res) { 3673 /* amd vsdb found */ 3674 vsdb_info->freesync_supported = 1; 3675 vsdb_info->amd_vsdb_version = version; 3676 vsdb_info->min_refresh_rate_hz = min_rate; 3677 vsdb_info->max_refresh_rate_hz = max_rate; 3678 /* Not enabled on DMCU*/ 3679 vsdb_info->freesync_mccs_vcp_code = 0; 3680 return true; 3681 } 3682 /* not amd vsdb */ 3683 return false; 3684 } 3685 3686 /* check for ack*/ 3687 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 3688 if (!res) 3689 return false; 3690 } 3691 3692 return false; 3693 } 3694 3695 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 3696 u8 *edid_ext, int len, 3697 struct amdgpu_hdmi_vsdb_info *vsdb_info) 3698 { 3699 int i; 3700 3701 /* send extension block to DMCU for parsing */ 3702 for (i = 0; i < len; i += 8) { 3703 /* send 8 bytes a time */ 3704 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 3705 return false; 3706 } 3707 3708 return vsdb_info->freesync_supported; 3709 } 3710 3711 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 3712 u8 *edid_ext, int len, 3713 struct amdgpu_hdmi_vsdb_info *vsdb_info) 3714 { 3715 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 3716 bool ret; 3717 3718 mutex_lock(&adev->dm.dc_lock); 3719 if (adev->dm.dmub_srv) 3720 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 3721 else 3722 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 3723 mutex_unlock(&adev->dm.dc_lock); 3724 return ret; 3725 } 3726 3727 STATIC_IFN_KUNIT void parse_edid_displayid_vrr(struct drm_connector *connector, 3728 const struct edid *edid) 3729 { 3730 u8 *edid_ext = NULL; 3731 int i; 3732 int j = 0; 3733 u16 min_vfreq; 3734 u16 max_vfreq; 3735 3736 if (!edid || !edid->extensions) 3737 return; 3738 3739 /* Find DisplayID extension */ 3740 for (i = 0; i < edid->extensions; i++) { 3741 edid_ext = (void *)(edid + (i + 1)); 3742 if (edid_ext[0] == DISPLAYID_EXT) 3743 break; 3744 } 3745 3746 if (i == edid->extensions) 3747 return; 3748 3749 while (j < EDID_LENGTH) { 3750 /* Get dynamic video timing range from DisplayID if available */ 3751 if (EDID_LENGTH - j > 13 && edid_ext[j] == 0x25 && 3752 (edid_ext[j+1] & 0xFE) == 0 && (edid_ext[j+2] == 9)) { 3753 min_vfreq = edid_ext[j+9]; 3754 if (edid_ext[j+1] & 7) 3755 max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] & 3) << 8); 3756 else 3757 max_vfreq = edid_ext[j+10]; 3758 3759 if (max_vfreq && min_vfreq) { 3760 connector->display_info.monitor_range.max_vfreq = max_vfreq; 3761 connector->display_info.monitor_range.min_vfreq = min_vfreq; 3762 3763 return; 3764 } 3765 } 3766 j++; 3767 } 3768 } 3769 EXPORT_IF_KUNIT(parse_edid_displayid_vrr); 3770 3771 STATIC_IFN_KUNIT int get_amd_vsdb(struct amdgpu_dm_connector *aconnector, 3772 struct amdgpu_hdmi_vsdb_info *vsdb_info) 3773 { 3774 struct drm_connector *connector = &aconnector->base; 3775 3776 vsdb_info->replay_mode = connector->display_info.amd_vsdb.replay_mode; 3777 vsdb_info->amd_vsdb_version = connector->display_info.amd_vsdb.version; 3778 3779 return connector->display_info.amd_vsdb.version != 0; 3780 } 3781 EXPORT_IF_KUNIT(get_amd_vsdb); 3782 3783 STATIC_IFN_KUNIT int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 3784 const struct edid *edid, 3785 struct amdgpu_hdmi_vsdb_info *vsdb_info) 3786 { 3787 u8 *edid_ext = NULL; 3788 int i; 3789 bool valid_vsdb_found = false; 3790 3791 /*----- drm_find_cea_extension() -----*/ 3792 /* No EDID or EDID extensions */ 3793 if (edid == NULL || edid->extensions == 0) 3794 return -ENODEV; 3795 3796 /* Find CEA extension */ 3797 for (i = 0; i < edid->extensions; i++) { 3798 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 3799 if (edid_ext[0] == CEA_EXT) 3800 break; 3801 } 3802 3803 if (i == edid->extensions) 3804 return -ENODEV; 3805 3806 /*----- cea_db_offsets() -----*/ 3807 if (edid_ext[0] != CEA_EXT) 3808 return -ENODEV; 3809 3810 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 3811 3812 return valid_vsdb_found ? i : -ENODEV; 3813 } 3814 EXPORT_IF_KUNIT(parse_hdmi_amd_vsdb); 3815 3816 /** 3817 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 3818 * 3819 * @connector: Connector to query. 3820 * @drm_edid: DRM EDID from monitor 3821 * @do_mccs: Controls whether MCCS (Monitor Control Command Set) over 3822 * DDC (Display Data Channel) transactions are performed. When true, 3823 * the driver queries the monitor to get or update additional FreeSync 3824 * capability information. When false, these transactions are skipped. 3825 * 3826 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 3827 * track of some of the display information in the internal data struct used by 3828 * amdgpu_dm. This function checks which type of connector we need to set the 3829 * FreeSync parameters. 3830 */ 3831 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 3832 const struct drm_edid *drm_edid, bool do_mccs) 3833 { 3834 int i = 0; 3835 struct amdgpu_dm_connector *amdgpu_dm_connector = 3836 to_amdgpu_dm_connector(connector); 3837 struct dm_connector_state *dm_con_state = NULL; 3838 struct dc_sink *sink; 3839 struct amdgpu_device *adev = drm_to_adev(connector->dev); 3840 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 3841 const struct edid *edid; 3842 bool freesync_capable = false; 3843 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 3844 3845 if (!connector->state) { 3846 drm_err(adev_to_drm(adev), "%s - Connector has no state", __func__); 3847 goto update; 3848 } 3849 3850 sink = amdgpu_dm_connector->dc_sink ? 3851 amdgpu_dm_connector->dc_sink : 3852 amdgpu_dm_connector->dc_em_sink; 3853 3854 drm_edid_connector_update(connector, drm_edid); 3855 3856 if (!drm_edid || !sink) { 3857 dm_con_state = to_dm_connector_state(connector->state); 3858 3859 amdgpu_dm_connector->min_vfreq = 0; 3860 amdgpu_dm_connector->max_vfreq = 0; 3861 freesync_capable = false; 3862 3863 goto update; 3864 } 3865 3866 dm_con_state = to_dm_connector_state(connector->state); 3867 3868 if (!adev->dm.freesync_module || !dc_supports_vrr(sink->ctx->dce_version)) 3869 goto update; 3870 3871 /* FIXME: Get rid of drm_edid_raw() */ 3872 edid = drm_edid_raw(drm_edid); 3873 3874 /* Some eDP panels only have the refresh rate range info in DisplayID */ 3875 if ((connector->display_info.monitor_range.min_vfreq == 0 || 3876 connector->display_info.monitor_range.max_vfreq == 0)) 3877 parse_edid_displayid_vrr(connector, edid); 3878 3879 if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 3880 sink->sink_signal == SIGNAL_TYPE_EDP)) { 3881 if (amdgpu_dm_connector->dc_link && 3882 amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) { 3883 amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; 3884 amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; 3885 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 3886 freesync_capable = true; 3887 } 3888 3889 get_amd_vsdb(amdgpu_dm_connector, &vsdb_info); 3890 3891 if (vsdb_info.replay_mode) { 3892 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; 3893 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; 3894 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; 3895 } 3896 3897 } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 3898 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 3899 if (i >= 0) { 3900 amdgpu_dm_connector->vsdb_info = vsdb_info; 3901 sink->edid_caps.freesync_vcp_code = vsdb_info.freesync_mccs_vcp_code; 3902 3903 if (vsdb_info.freesync_supported) { 3904 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 3905 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 3906 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 3907 freesync_capable = true; 3908 3909 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 3910 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 3911 } 3912 } 3913 } 3914 3915 if (amdgpu_dm_connector->dc_link) 3916 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 3917 3918 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 3919 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 3920 if (i >= 0) { 3921 amdgpu_dm_connector->vsdb_info = vsdb_info; 3922 sink->edid_caps.freesync_vcp_code = vsdb_info.freesync_mccs_vcp_code; 3923 3924 if (vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 3925 amdgpu_dm_connector->pack_sdp_v1_3 = true; 3926 amdgpu_dm_connector->as_type = as_type; 3927 3928 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 3929 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 3930 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 3931 freesync_capable = true; 3932 3933 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 3934 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 3935 } 3936 } 3937 } 3938 3939 /* Handle MCCS */ 3940 if (do_mccs) 3941 dm_helpers_read_mccs_caps(adev->dm.dc->ctx, amdgpu_dm_connector->dc_link, sink); 3942 3943 if ((sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A || 3944 as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) && 3945 (!sink->edid_caps.freesync_vcp_code || 3946 (sink->edid_caps.freesync_vcp_code && !sink->mccs_caps.freesync_supported))) 3947 freesync_capable = false; 3948 3949 if (do_mccs && sink->mccs_caps.freesync_supported && freesync_capable) 3950 dm_helpers_mccs_vcp_set(adev->dm.dc->ctx, amdgpu_dm_connector->dc_link, sink); 3951 3952 update: 3953 if (dm_con_state) 3954 dm_con_state->freesync_capable = freesync_capable; 3955 3956 if (connector->state && amdgpu_dm_connector->dc_link && !freesync_capable && 3957 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) { 3958 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false; 3959 amdgpu_dm_connector->dc_link->replay_settings.replay_feature_enabled = false; 3960 } 3961 3962 if (connector->vrr_capable_property) 3963 drm_connector_set_vrr_capable_property(connector, 3964 freesync_capable); 3965 } 3966