| /linux/drivers/mailbox/ |
| H A D | stm32-ipcc.c | 84 struct stm32_ipcc *ipcc = data; in stm32_ipcc_rx_irq() local
85 struct device *dev = ipcc->controller.dev; in stm32_ipcc_rx_irq()
91 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; in stm32_ipcc_rx_irq()
92 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_rx_irq()
93 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq()
98 for (chan = 0; chan < ipcc->n_chans; chan++) { in stm32_ipcc_rx_irq()
104 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL); in stm32_ipcc_rx_irq()
106 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, in stm32_ipcc_rx_irq()
117 struct stm32_ipcc *ipcc = data; in stm32_ipcc_tx_irq() local
118 struct device *dev = ipcc->controller.dev; in stm32_ipcc_tx_irq()
[all …]
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| H A D | qcom-ipcc.c | 76 struct qcom_ipcc *ipcc = data; in qcom_ipcc_irq_fn() local
81 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); in qcom_ipcc_irq_fn()
85 virq = irq_find_mapping(ipcc->irq_domain, hwirq); in qcom_ipcc_irq_fn()
86 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); in qcom_ipcc_irq_fn()
95 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); in qcom_ipcc_mask_irq() local
98 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); in qcom_ipcc_mask_irq()
103 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); in qcom_ipcc_unmask_irq() local
106 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE); in qcom_ipcc_unmask_irq()
119 struct qcom_ipcc *ipcc = d->host_data; in qcom_ipcc_domain_map() local
122 irq_set_chip_data(irq, ipcc); in qcom_ipcc_domain_map()
[all …]
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp157a-microgea-stm32mp1.dtsi | 116 &ipcc {
128 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| H A D | stm32mp15xx-osd32.dtsi | 200 &ipcc {
207 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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| H A D | stm32mp15xx-dhcor-som.dtsi | 218 &ipcc {
230 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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| H A D | stm32mp157c-odyssey-som.dtsi | 221 &ipcc {
233 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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| H A D | stm32mp157a-icore-stm32mp1.dtsi | 164 &ipcc {
176 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| H A D | stm32mp157c-emstamp-argon.dtsi | 358 &ipcc {
370 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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| /linux/sound/soc/intel/catpt/ |
| H A D | ipc.c | 273 u32 isc, ipcc; in catpt_dsp_irq_handler()
283 ipcc = catpt_readl_shim(cdev, IPCC); in catpt_dsp_irq_handler()
284 trace_catpt_ipc_reply(ipcc); in catpt_dsp_irq_handler()
285 catpt_dsp_copy_rx(cdev, ipcc); in catpt_dsp_irq_handler()
268 u32 isc, ipcc; catpt_dsp_irq_handler() local
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| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | monaco.dtsi | 19 #include <dt-bindings/mailbox/qcom-ipcc.h>
838 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
841 mboxes = <&ipcc IPCC_CLIENT_LPASS
862 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
865 mboxes = <&ipcc IPCC_CLIENT_CDSP
886 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
889 mboxes = <&ipcc IPCC_CLIENT_GPDSP0
932 ipcc: mailbox@408000 { label
933 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
2799 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
[all …]
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| H A D | hamoa.dtsi | 17 #include <dt-bindings/mailbox/qcom-ipcc.h>
752 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
756 mboxes = <&ipcc IPCC_CLIENT_LPASS
778 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
782 mboxes = <&ipcc IPCC_CLIENT_CDSP
860 ipcc: mailbox@408000 { label
861 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
4361 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4364 mboxes = <&ipcc IPCC_CLIENT_LPASS
6116 interrupt-parent = <&ipcc>;
[all …]
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| /linux/ |
| H A D | MAINTAINERS | 22006 F: Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
22007 F: drivers/mailbox/qcom-ipcc.c
22008 F: include/dt-bindings/mailbox/qcom-ipcc.h
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