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Searched refs:gt (Results 1 – 25 of 202) sorted by relevance

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/linux/drivers/gpu/drm/xe/
H A Dxe_gt_sriov_pf_migration.c32 static struct xe_gt_sriov_migration_data *pf_pick_gt_migration(struct xe_gt *gt, unsigned int vfid) in pf_pick_gt_migration() argument
34 xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); in pf_pick_gt_migration()
35 xe_gt_assert(gt, vfid != PFID); in pf_pick_gt_migration()
36 xe_gt_assert(gt, vfid <= xe_sriov_pf_get_totalvfs(gt_to_xe(gt))); in pf_pick_gt_migration()
38 return &gt->sriov.pf.vfs[vfid].migration; in pf_pick_gt_migration()
41 static void pf_dump_mig_data(struct xe_gt *gt, unsigned int vfid, in pf_dump_mig_data() argument
46 struct drm_printer p = xe_gt_dbg_printer(gt); in pf_dump_mig_data()
54 static ssize_t pf_migration_ggtt_size(struct xe_gt *gt, unsigned int vfid) in pf_migration_ggtt_size() argument
56 if (!xe_gt_is_main_type(gt)) in pf_migration_ggtt_size()
59 return xe_gt_sriov_pf_config_ggtt_save(gt, vfid, NULL, 0); in pf_migration_ggtt_size()
[all …]
H A Dxe_gt_debugfs.c84 struct xe_gt *gt = node_to_gt(node); in xe_gt_debugfs_simple_show() local
90 return print(gt, &p); in xe_gt_debugfs_simple_show()
105 struct xe_gt *gt = node_to_gt(node); in xe_gt_debugfs_show_with_rpm() local
106 struct xe_device *xe = gt_to_xe(gt); in xe_gt_debugfs_show_with_rpm()
112 static int hw_engines(struct xe_gt *gt, struct drm_printer *p) in hw_engines() argument
117 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); in hw_engines()
121 for_each_hw_engine(hwe, gt, id) in hw_engines()
127 static int steering(struct xe_gt *gt, struct drm_printer *p) in steering() argument
129 xe_gt_mcr_steering_dump(gt, p); in steering()
133 static int register_save_restore(struct xe_gt *gt, struct drm_printer *p) in register_save_restore() argument
[all …]
H A Dxe_gt_ccs_mode.c19 static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) in __xe_gt_apply_ccs_mode() argument
22 int num_slices = hweight32(CCS_INSTANCES(gt)); in __xe_gt_apply_ccs_mode()
23 struct xe_device *xe = gt_to_xe(gt); in __xe_gt_apply_ccs_mode()
27 xe_assert(xe, xe_gt_ccs_mode_enabled(gt)); in __xe_gt_apply_ccs_mode()
54 for_each_hw_engine(hwe, gt, id) { in __xe_gt_apply_ccs_mode()
64 while ((CCS_INSTANCES(gt) & BIT(cslice)) == 0) in __xe_gt_apply_ccs_mode()
79 xe_mmio_write32(&gt->mmio, CCS_MODE, mode); in __xe_gt_apply_ccs_mode()
81 xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n", in __xe_gt_apply_ccs_mode()
85 void xe_gt_apply_ccs_mode(struct xe_gt *gt) in xe_gt_apply_ccs_mode() argument
87 if (!gt->ccs_mode || IS_SRIOV_VF(gt_to_xe(gt))) in xe_gt_apply_ccs_mode()
[all …]
H A Dxe_hw_engine.c282 hwe->gt = NULL; in hw_engine_fini()
297 xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); in xe_hw_engine_mmio_read32()
298 xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain); in xe_hw_engine_mmio_read32()
302 return xe_mmio_read32(&hwe->gt->mmio, reg); in xe_hw_engine_mmio_read32()
307 xe_mmio_write32(&hwe->gt->mmio, RING_HWS_PGA(hwe->mmio_base), in xe_hw_engine_enable_ring()
312 const struct xe_gt *gt, in xe_hw_engine_match_fixed_cslice_mode() argument
319 if (GRAPHICS_VER(gt_to_xe(gt)) >= 35) in xe_hw_engine_match_fixed_cslice_mode()
322 return xe_gt_ccs_mode_enabled(gt) && in xe_hw_engine_match_fixed_cslice_mode()
323 xe_rtp_match_first_render_or_compute(xe, gt, hwe); in xe_hw_engine_match_fixed_cslice_mode()
327 const struct xe_gt *gt, in xe_rtp_cfeg_wmtp_disabled() argument
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H A Dxe_gt_idle.c54 struct xe_gt *gt = container_of(guc, struct xe_gt, uc.guc); in pc_to_xe() local
56 return gt_to_xe(gt); in pc_to_xe()
103 void xe_gt_idle_enable_pg(struct xe_gt *gt) in xe_gt_idle_enable_pg() argument
105 struct xe_device *xe = gt_to_xe(gt); in xe_gt_idle_enable_pg()
106 struct xe_gt_idle *gtidle = &gt->gtidle; in xe_gt_idle_enable_pg()
107 struct xe_mmio *mmio = &gt->mmio; in xe_gt_idle_enable_pg()
118 xe_device_assert_mem_access(gt_to_xe(gt)); in xe_gt_idle_enable_pg()
120 vcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_DECODE); in xe_gt_idle_enable_pg()
121 vecs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE); in xe_gt_idle_enable_pg()
126 if (xe_gt_is_main_type(gt)) in xe_gt_idle_enable_pg()
[all …]
H A Dxe_rtp.c35 struct xe_gt *gt; member
51 struct xe_gt *gt = match_ctx->gt; in rule_match_item() local
68 if (drm_WARN_ON(&xe->drm, !gt)) in rule_match_item()
72 (!has_samedia(xe) || !xe_gt_is_media_type(gt)); in rule_match_item()
74 if (drm_WARN_ON(&xe->drm, !gt)) in rule_match_item()
79 (!has_samedia(xe) || !xe_gt_is_media_type(gt)); in rule_match_item()
81 if (drm_WARN_ON(&xe->drm, !gt)) in rule_match_item()
86 if (drm_WARN_ON(&xe->drm, !gt)) in rule_match_item()
91 (!has_samedia(xe) || !xe_gt_is_media_type(gt)); in rule_match_item()
93 if (drm_WARN_ON(&xe->drm, !gt)) in rule_match_item()
[all …]
H A Dxe_gt_sriov_pf_monitor.c24 void xe_gt_sriov_pf_monitor_flr(struct xe_gt *gt, u32 vfid) in xe_gt_sriov_pf_monitor_flr() argument
28 xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); in xe_gt_sriov_pf_monitor_flr()
29 xe_gt_sriov_pf_assert_vfid(gt, vfid); in xe_gt_sriov_pf_monitor_flr()
32 gt->sriov.pf.vfs[vfid].monitor.guc.events[e] = 0; in xe_gt_sriov_pf_monitor_flr()
35 static void pf_update_event_counter(struct xe_gt *gt, u32 vfid, in pf_update_event_counter() argument
38 xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); in pf_update_event_counter()
39 xe_gt_assert(gt, e < XE_GUC_KLV_NUM_THRESHOLDS); in pf_update_event_counter()
41 gt->sriov.pf.vfs[vfid].monitor.guc.events[e]++; in pf_update_event_counter()
44 static int pf_handle_vf_threshold_event(struct xe_gt *gt, u32 vfid, u32 threshold) in pf_handle_vf_threshold_event() argument
54 xe_gt_sriov_notice(gt, "unknown threshold key %#x reported for %s\n", in pf_handle_vf_threshold_event()
[all …]
H A Dxe_gsc.c47 struct xe_gt *gt = gsc_to_gt(gsc); in memcpy_fw() local
48 struct xe_device *xe = gt_to_xe(gt); in memcpy_fw()
72 struct xe_gt *gt = gsc_to_gt(gsc); in emit_gsc_upload() local
79 bb = xe_bb_new(gt, 4, false); in emit_gsc_upload()
130 struct xe_gt *gt = gsc_to_gt(gsc); in query_compatibility_version() local
131 struct xe_tile *tile = gt_to_tile(gt); in query_compatibility_version()
132 struct xe_device *xe = gt_to_xe(gt); in query_compatibility_version()
144 xe_gt_err(gt, "failed to allocate bo for GSC version query\n"); in query_compatibility_version()
158 xe_gt_err(gt, in query_compatibility_version()
168 xe_gt_err(gt, "HuC: invalid GSC reply for version query (err=%d)\n", err); in query_compatibility_version()
[all …]
H A Dxe_gsc_proxy.c68 struct xe_gt *gt = gsc_to_gt(gsc); in xe_gsc_proxy_init_done() local
69 u32 fwsts1 = xe_mmio_read32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)); in xe_gsc_proxy_init_done()
77 struct xe_gt *gt = gsc_to_gt(gsc); in xe_gsc_wait_for_proxy_init_done() local
80 return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE), in xe_gsc_wait_for_proxy_init_done()
88 struct xe_gt *gt = gsc_to_gt(gsc); in __gsc_proxy_irq_rmw() local
93 xe_mmio_rmw32(&gt->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE), clr, set); in __gsc_proxy_irq_rmw()
112 struct xe_gt *gt = gsc_to_gt(gsc); in proxy_send_to_csme() local
118 xe_gt_err(gt, "Failed to send CSME proxy message\n"); in proxy_send_to_csme()
124 xe_gt_err(gt, "Failed to receive CSME proxy message\n"); in proxy_send_to_csme()
133 struct xe_gt *gt = gsc_to_gt(gsc); in proxy_send_to_gsc() local
[all …]
H A Dxe_guc_ads.c215 static size_t calculate_regset_size(struct xe_gt *gt) in calculate_regset_size() argument
223 for_each_hw_engine(hwe, gt, id) in calculate_regset_size()
229 if (XE_GT_WA(gt, 1607983814)) in calculate_regset_size()
257 static u32 engine_enable_mask(struct xe_gt *gt, u16 guc_class) in engine_enable_mask() argument
263 for_each_hw_engine(hwe, gt, id) in engine_enable_mask()
269 xe_gt_assert(gt, !mask || is_power_of_2(mask)); in engine_enable_mask()
276 struct xe_gt *gt = ads_to_gt(ads); in calculate_golden_lrc_size() local
284 if (!engine_enable_mask(gt, guc_class)) in calculate_golden_lrc_size()
287 real_size = xe_gt_lrc_size(gt, class); in calculate_golden_lrc_size()
321 struct xe_gt *gt = ads_to_gt(ads); in guc_waklv_init() local
[all …]
H A Dxe_gt_sysfs.c27 struct xe_gt *gt = arg; in gt_sysfs_fini() local
29 kobject_put(gt->sysfs); in gt_sysfs_fini()
32 int xe_gt_sysfs_init(struct xe_gt *gt) in xe_gt_sysfs_init() argument
34 struct xe_tile *tile = gt_to_tile(gt); in xe_gt_sysfs_init()
35 struct xe_device *xe = gt_to_xe(gt); in xe_gt_sysfs_init()
44 kg->gt = gt; in xe_gt_sysfs_init()
46 err = kobject_add(&kg->base, tile->sysfs, "gt%d", gt->info.id); in xe_gt_sysfs_init()
52 gt->sysfs = &kg->base; in xe_gt_sysfs_init()
54 return devm_add_action_or_reset(xe->drm.dev, gt_sysfs_fini, gt); in xe_gt_sysfs_init()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt.h20 #define IS_GFX_GT_IP_RANGE(gt, from, until) ( \ argument
23 ((gt)->type != GT_MEDIA && \
24 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
25 GRAPHICS_VER_FULL((gt)->i915) <= (until)))
34 #define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \ argument
37 ((gt) && (gt)->type == GT_MEDIA && \
38 MEDIA_VER_FULL((gt)->i915) >= (from) && \
39 MEDIA_VER_FULL((gt)->i915) <= (until)))
56 #define IS_GFX_GT_IP_STEP(gt, ipver, from, until) ( \ argument
58 (IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
[all …]
H A Dselftest_reset.c18 __igt_reset_stolen(struct intel_gt *gt, in __igt_reset_stolen() argument
22 struct i915_ggtt *ggtt = gt->ggtt; in __igt_reset_stolen()
23 const struct resource *dsm = &gt->i915->dsm.stolen; in __igt_reset_stolen()
51 igt_global_reset_lock(gt); in __igt_reset_stolen()
52 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in __igt_reset_stolen()
54 err = igt_spinner_init(&spin, gt); in __igt_reset_stolen()
58 for_each_engine(engine, gt, id) { in __igt_reset_stolen()
89 i915_gem_get_pat_index(gt->i915, in __igt_reset_stolen()
98 if (!__drm_mm_interval_first(&gt->i915->mm.stolen, in __igt_reset_stolen()
114 intel_gt_reset(gt, mask, NULL); in __igt_reset_stolen()
[all …]
H A Dintel_gt_pm_irq.c13 static void write_pm_imr(struct intel_gt *gt) in write_pm_imr() argument
15 struct drm_i915_private *i915 = gt->i915; in write_pm_imr()
16 struct intel_uncore *uncore = gt->uncore; in write_pm_imr()
17 u32 mask = gt->pm_imr; in write_pm_imr()
32 static void gen6_gt_pm_update_irq(struct intel_gt *gt, in gen6_gt_pm_update_irq() argument
40 lockdep_assert_held(gt->irq_lock); in gen6_gt_pm_update_irq()
42 new_val = gt->pm_imr; in gen6_gt_pm_update_irq()
46 if (new_val != gt->pm_imr) { in gen6_gt_pm_update_irq()
47 gt->pm_imr = new_val; in gen6_gt_pm_update_irq()
48 write_pm_imr(gt); in gen6_gt_pm_update_irq()
[all …]
H A Dintel_gt_sysfs.c49 static struct kobject *gt_get_parent_obj(struct intel_gt *gt) in gt_get_parent_obj() argument
51 return &gt->i915->drm.primary->kdev->kobj; in gt_get_parent_obj()
58 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name); in id_show() local
60 return sysfs_emit(buf, "%u\n", gt->info.id); in id_show()
81 void intel_gt_sysfs_register(struct intel_gt *gt) in intel_gt_sysfs_register() argument
91 if (gt_is_root(gt)) in intel_gt_sysfs_register()
92 intel_gt_sysfs_pm_init(gt, gt_get_parent_obj(gt)); in intel_gt_sysfs_register()
95 if (kobject_init_and_add(&gt->sysfs_gt, &kobj_gt_type, in intel_gt_sysfs_register()
96 gt->i915->sysfs_gt, "gt%d", gt->info.id)) in intel_gt_sysfs_register()
99 gt->sysfs_defaults = kobject_create_and_add(".defaults", &gt->sysfs_gt); in intel_gt_sysfs_register()
[all …]
H A Dselftest_slpc.c22 struct intel_gt *gt; member
53 static int slpc_set_freq(struct intel_gt *gt, u32 freq) in slpc_set_freq() argument
56 struct intel_guc_slpc *slpc = &gt_to_guc(gt)->slpc; in slpc_set_freq()
113 static u64 measure_power_at_freq(struct intel_gt *gt, int *freq, u64 *power) in measure_power_at_freq() argument
117 err = slpc_set_freq(gt, *freq); in measure_power_at_freq()
120 *freq = intel_rps_read_actual_frequency(&gt->rps); in measure_power_at_freq()
121 *power = slpc_measure_power(&gt->rps, freq); in measure_power_at_freq()
198 static int slpc_power(struct intel_gt *gt, struct intel_engine_cs *engine) in slpc_power() argument
200 struct intel_guc_slpc *slpc = &gt_to_guc(gt)->slpc; in slpc_power()
212 if (!librapl_supported(gt->i915)) in slpc_power()
[all …]
H A Dselftest_hangcheck.c33 struct intel_gt *gt; member
41 static int hang_init(struct hang *h, struct intel_gt *gt) in hang_init() argument
47 h->gt = gt; in hang_init()
49 h->ctx = kernel_context(gt->i915, NULL); in hang_init()
55 h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
61 h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
76 intel_gt_coherent_map_type(gt, h->obj, false)); in hang_init()
106 struct intel_gt *gt = h->gt; in hang_create_request() local
116 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_create_request()
122 vaddr = i915_gem_object_pin_map_unlocked(obj, intel_gt_coherent_map_type(gt, obj, false)); in hang_create_request()
[all …]
H A Dselftest_gt_pm.c81 struct intel_gt *gt = arg; in live_gt_clocks() local
87 if (!gt->clock_frequency) { /* unknown */ in live_gt_clocks()
92 if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */ in live_gt_clocks()
95 wakeref = intel_gt_pm_get(gt); in live_gt_clocks()
96 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); in live_gt_clocks()
98 for_each_engine(engine, gt, id) { in live_gt_clocks()
109 time = intel_gt_clock_interval_to_ns(engine->gt, cycles); in live_gt_clocks()
110 expected = intel_gt_ns_to_clock_interval(engine->gt, dt); in live_gt_clocks()
114 engine->gt->clock_frequency / 1000); in live_gt_clocks()
131 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); in live_gt_clocks()
[all …]
H A Dintel_gt_irq.h23 void gen11_gt_irq_reset(struct intel_gt *gt);
24 void gen11_gt_irq_postinstall(struct intel_gt *gt);
25 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl);
27 bool gen11_gt_reset_one_iir(struct intel_gt *gt,
31 void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
33 void gen5_gt_irq_postinstall(struct intel_gt *gt);
34 void gen5_gt_irq_reset(struct intel_gt *gt);
35 void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask);
36 void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);
38 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
[all …]
H A Dintel_gt_mcr.h11 void intel_gt_mcr_init(struct intel_gt *gt);
12 void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags);
13 void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags);
14 void intel_gt_mcr_lock_sanitize(struct intel_gt *gt);
16 u32 intel_gt_mcr_read(struct intel_gt *gt,
19 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg);
20 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg);
22 void intel_gt_mcr_unicast_write(struct intel_gt *gt,
25 void intel_gt_mcr_multicast_write(struct intel_gt *gt,
27 void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt,
[all …]
H A Dintel_engine_cs.c273 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) in intel_engine_context_size() argument
275 struct intel_uncore *uncore = gt->uncore; in intel_engine_context_size()
284 switch (GRAPHICS_VER(gt->i915)) { in intel_engine_context_size()
286 MISSING_CASE(GRAPHICS_VER(gt->i915)); in intel_engine_context_size()
296 if (IS_HASWELL(gt->i915)) in intel_engine_context_size()
319 gt_dbg(gt, "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n", in intel_engine_context_size()
320 GRAPHICS_VER(gt->i915), cxt_size * 64, in intel_engine_context_size()
337 if (GRAPHICS_VER(gt->i915) < 8) in intel_engine_context_size()
449 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, in intel_engine_setup() argument
453 struct drm_i915_private *i915 = gt->i915; in intel_engine_setup()
[all …]
H A Dselftest_rc6.c34 struct intel_gt *gt = arg; in live_rc6_manual() local
35 struct intel_rc6 *rc6 = &gt->rc6; in live_rc6_manual()
36 struct intel_rps *rps = &gt->rps; in live_rc6_manual()
62 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
65 has_power = librapl_supported(gt->i915); in live_rc6_manual()
66 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in live_rc6_manual()
118 intel_uncore_read_fw(gt->uncore, GEN6_RC_STATE), in live_rc6_manual()
119 intel_uncore_read_fw(gt->uncore, GEN6_RC_CONTROL), in live_rc6_manual()
152 intel_runtime_pm_put(gt->uncore->rpm, wakeref); in live_rc6_manual()
190 randomised_engines(struct intel_gt *gt, in randomised_engines() argument
[all …]
/linux/drivers/gpu/drm/i915/selftests/
H A Digt_reset.c14 void igt_global_reset_lock(struct intel_gt *gt) in igt_global_reset_lock() argument
19 pr_debug("%s: current gpu_error=%08lx\n", __func__, gt->reset.flags); in igt_global_reset_lock()
21 while (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) in igt_global_reset_lock()
22 wait_event(gt->reset.queue, in igt_global_reset_lock()
23 !test_bit(I915_RESET_BACKOFF, &gt->reset.flags)); in igt_global_reset_lock()
25 for_each_engine(engine, gt, id) { in igt_global_reset_lock()
27 &gt->reset.flags)) in igt_global_reset_lock()
28 wait_on_bit(&gt->reset.flags, I915_RESET_ENGINE + id, in igt_global_reset_lock()
33 void igt_global_reset_unlock(struct intel_gt *gt) in igt_global_reset_unlock() argument
38 for_each_engine(engine, gt, id) in igt_global_reset_unlock()
[all …]
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_gsc_uc.c19 struct intel_gt *gt = gsc_uc_to_gt(gsc); in gsc_work() local
24 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in gsc_work()
26 spin_lock_irq(gt->irq_lock); in gsc_work()
29 spin_unlock_irq(gt->irq_lock); in gsc_work()
53 if (intel_uc_uses_huc(&gt->uc) && in gsc_work()
54 intel_huc_is_authenticated(&gt->uc.huc, INTEL_HUC_AUTH_BY_GUC)) in gsc_work()
55 intel_huc_auth(&gt->uc.huc, INTEL_HUC_AUTH_BY_GSC); in gsc_work()
60 gt_err(gt, "Proxy request received with GSC not loaded!\n"); in gsc_work()
71 gt_err(gt, "GSC proxy handler failed to init\n"); in gsc_work()
85 gt_dbg(gt, "GSC Proxy initialized\n"); in gsc_work()
[all …]
H A Dintel_guc_ads.c163 struct intel_gt *gt = guc_to_gt(guc); in guc_policies_init() local
164 struct drm_i915_private *i915 = gt->i915; in guc_policies_init()
206 struct intel_gt *gt = guc_to_gt(guc); in intel_guc_global_policies_update() local
222 with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref) in intel_guc_global_policies_update()
228 static void guc_mapping_table_init(struct intel_gt *gt, in guc_mapping_table_init() argument
241 for_each_engine(engine, gt, id) { in guc_mapping_table_init()
301 static long __must_check guc_mmio_reg_add(struct intel_gt *gt, in guc_mmio_reg_add() argument
337 #define GUC_MMIO_REG_ADD(gt, regset, reg, masked) \ argument
338 guc_mmio_reg_add(gt, \
349 static long __must_check guc_mcr_reg_add(struct intel_gt *gt, in guc_mcr_reg_add() argument
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