124f90d66SChris Wilson // SPDX-License-Identifier: MIT
2d762043fSAndi Shyti /*
3d762043fSAndi Shyti * Copyright © 2019 Intel Corporation
4d762043fSAndi Shyti */
5d762043fSAndi Shyti
6d762043fSAndi Shyti #include "i915_drv.h"
7d762043fSAndi Shyti #include "i915_reg.h"
8d762043fSAndi Shyti #include "intel_gt.h"
9cf1c97dcSAndi Shyti #include "intel_gt_irq.h"
10d762043fSAndi Shyti #include "intel_gt_pm_irq.h"
110d6419e9SMatt Roper #include "intel_gt_regs.h"
12d762043fSAndi Shyti
write_pm_imr(struct intel_gt * gt)13d762043fSAndi Shyti static void write_pm_imr(struct intel_gt *gt)
14d762043fSAndi Shyti {
15d762043fSAndi Shyti struct drm_i915_private *i915 = gt->i915;
16d762043fSAndi Shyti struct intel_uncore *uncore = gt->uncore;
17d762043fSAndi Shyti u32 mask = gt->pm_imr;
18d762043fSAndi Shyti i915_reg_t reg;
19d762043fSAndi Shyti
20c816723bSLucas De Marchi if (GRAPHICS_VER(i915) >= 11) {
21d762043fSAndi Shyti reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
22d762043fSAndi Shyti mask <<= 16; /* pm is in upper half */
23c816723bSLucas De Marchi } else if (GRAPHICS_VER(i915) >= 8) {
24d762043fSAndi Shyti reg = GEN8_GT_IMR(2);
25d762043fSAndi Shyti } else {
26d762043fSAndi Shyti reg = GEN6_PMIMR;
27d762043fSAndi Shyti }
28d762043fSAndi Shyti
29d762043fSAndi Shyti intel_uncore_write(uncore, reg, mask);
30d762043fSAndi Shyti }
31d762043fSAndi Shyti
gen6_gt_pm_update_irq(struct intel_gt * gt,u32 interrupt_mask,u32 enabled_irq_mask)32d762043fSAndi Shyti static void gen6_gt_pm_update_irq(struct intel_gt *gt,
33d762043fSAndi Shyti u32 interrupt_mask,
34d762043fSAndi Shyti u32 enabled_irq_mask)
35d762043fSAndi Shyti {
36d762043fSAndi Shyti u32 new_val;
37d762043fSAndi Shyti
38d762043fSAndi Shyti WARN_ON(enabled_irq_mask & ~interrupt_mask);
39d762043fSAndi Shyti
40*03d2c54dSMatt Roper lockdep_assert_held(gt->irq_lock);
41d762043fSAndi Shyti
42d762043fSAndi Shyti new_val = gt->pm_imr;
43d762043fSAndi Shyti new_val &= ~interrupt_mask;
44d762043fSAndi Shyti new_val |= ~enabled_irq_mask & interrupt_mask;
45d762043fSAndi Shyti
46d762043fSAndi Shyti if (new_val != gt->pm_imr) {
47d762043fSAndi Shyti gt->pm_imr = new_val;
48d762043fSAndi Shyti write_pm_imr(gt);
49d762043fSAndi Shyti }
50d762043fSAndi Shyti }
51d762043fSAndi Shyti
gen6_gt_pm_unmask_irq(struct intel_gt * gt,u32 mask)52d762043fSAndi Shyti void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask)
53d762043fSAndi Shyti {
54d762043fSAndi Shyti gen6_gt_pm_update_irq(gt, mask, mask);
55d762043fSAndi Shyti }
56d762043fSAndi Shyti
gen6_gt_pm_mask_irq(struct intel_gt * gt,u32 mask)57d762043fSAndi Shyti void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
58d762043fSAndi Shyti {
59d762043fSAndi Shyti gen6_gt_pm_update_irq(gt, mask, 0);
60d762043fSAndi Shyti }
61d762043fSAndi Shyti
gen6_gt_pm_reset_iir(struct intel_gt * gt,u32 reset_mask)62d762043fSAndi Shyti void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
63d762043fSAndi Shyti {
64d762043fSAndi Shyti struct intel_uncore *uncore = gt->uncore;
65c816723bSLucas De Marchi i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
66d762043fSAndi Shyti
67*03d2c54dSMatt Roper lockdep_assert_held(gt->irq_lock);
68d762043fSAndi Shyti
69d762043fSAndi Shyti intel_uncore_write(uncore, reg, reset_mask);
70d762043fSAndi Shyti intel_uncore_write(uncore, reg, reset_mask);
71d762043fSAndi Shyti intel_uncore_posting_read(uncore, reg);
72d762043fSAndi Shyti }
73d762043fSAndi Shyti
write_pm_ier(struct intel_gt * gt)74d762043fSAndi Shyti static void write_pm_ier(struct intel_gt *gt)
75d762043fSAndi Shyti {
76d762043fSAndi Shyti struct drm_i915_private *i915 = gt->i915;
77d762043fSAndi Shyti struct intel_uncore *uncore = gt->uncore;
78d762043fSAndi Shyti u32 mask = gt->pm_ier;
79d762043fSAndi Shyti i915_reg_t reg;
80d762043fSAndi Shyti
81c816723bSLucas De Marchi if (GRAPHICS_VER(i915) >= 11) {
82d762043fSAndi Shyti reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
83d762043fSAndi Shyti mask <<= 16; /* pm is in upper half */
84c816723bSLucas De Marchi } else if (GRAPHICS_VER(i915) >= 8) {
85d762043fSAndi Shyti reg = GEN8_GT_IER(2);
86d762043fSAndi Shyti } else {
87d762043fSAndi Shyti reg = GEN6_PMIER;
88d762043fSAndi Shyti }
89d762043fSAndi Shyti
90d762043fSAndi Shyti intel_uncore_write(uncore, reg, mask);
91d762043fSAndi Shyti }
92d762043fSAndi Shyti
gen6_gt_pm_enable_irq(struct intel_gt * gt,u32 enable_mask)93d762043fSAndi Shyti void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
94d762043fSAndi Shyti {
95*03d2c54dSMatt Roper lockdep_assert_held(gt->irq_lock);
96d762043fSAndi Shyti
97d762043fSAndi Shyti gt->pm_ier |= enable_mask;
98d762043fSAndi Shyti write_pm_ier(gt);
99d762043fSAndi Shyti gen6_gt_pm_unmask_irq(gt, enable_mask);
100d762043fSAndi Shyti }
101d762043fSAndi Shyti
gen6_gt_pm_disable_irq(struct intel_gt * gt,u32 disable_mask)102d762043fSAndi Shyti void gen6_gt_pm_disable_irq(struct intel_gt *gt, u32 disable_mask)
103d762043fSAndi Shyti {
104*03d2c54dSMatt Roper lockdep_assert_held(gt->irq_lock);
105d762043fSAndi Shyti
106d762043fSAndi Shyti gt->pm_ier &= ~disable_mask;
107d762043fSAndi Shyti gen6_gt_pm_mask_irq(gt, disable_mask);
108d762043fSAndi Shyti write_pm_ier(gt);
109d762043fSAndi Shyti }
110