273 u32 intel_engine_context_size(struct intel_gt *gt, u8 class)  in intel_engine_context_size()  argument
275 	struct intel_uncore *uncore = gt->uncore;  in intel_engine_context_size()
284 		switch (GRAPHICS_VER(gt->i915)) {  in intel_engine_context_size()
286 			MISSING_CASE(GRAPHICS_VER(gt->i915));  in intel_engine_context_size()
296 			if (IS_HASWELL(gt->i915))  in intel_engine_context_size()
319 			gt_dbg(gt, "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",  in intel_engine_context_size()
320 			       GRAPHICS_VER(gt->i915), cxt_size * 64,  in intel_engine_context_size()
337 		if (GRAPHICS_VER(gt->i915) < 8)  in intel_engine_context_size()
449 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,  in intel_engine_setup()  argument
453 	struct drm_i915_private *i915 = gt->i915;  in intel_engine_setup()
462 	if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))  in intel_engine_setup()
471 	if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))  in intel_engine_setup()
484 	engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),  in intel_engine_setup()
487 	engine->gt = gt;  in intel_engine_setup()
488 	engine->uncore = gt->uncore;  in intel_engine_setup()
501 	    __ffs(CCS_MASK(engine->gt) | RCS_MASK(engine->gt)) == engine->instance)  in intel_engine_setup()
552 	engine->context_size = intel_engine_context_size(gt, engine->class);  in intel_engine_setup()
565 	gt->engine_class[info->class][info->instance] = engine;  in intel_engine_setup()
566 	gt->engine[id] = engine;  in intel_engine_setup()
591 	if (intel_guc_submission_is_wanted(gt_to_guc(engine->gt)))  in intel_clamp_preempt_timeout_ms()
612 	if (intel_guc_submission_is_wanted(gt_to_guc(engine->gt)))  in intel_clamp_timeslice_duration_ms()
639 		     (engine->gt->info.vdbox_sfc_access &  in __setup_engine_capabilities()
646 		    engine->gt->info.sfc_mask & BIT(engine->instance))  in __setup_engine_capabilities()
652 static void intel_setup_engine_capabilities(struct intel_gt *gt)  in intel_setup_engine_capabilities()  argument
657 	for_each_engine(engine, gt, id)  in intel_setup_engine_capabilities()
665 void intel_engines_release(struct intel_gt *gt)  in intel_engines_release()  argument
679 	GEM_BUG_ON(intel_gt_pm_is_awake(gt));  in intel_engines_release()
680 	if (!intel_gt_gpu_reset_clobbers_display(gt))  in intel_engines_release()
681 		intel_gt_reset_all_engines(gt);  in intel_engines_release()
684 	for_each_engine(engine, gt, id) {  in intel_engines_release()
697 	llist_del_all(&gt->i915->uabi_engines_llist);  in intel_engines_release()
708 void intel_engines_free(struct intel_gt *gt)  in intel_engines_free()  argument
716 	for_each_engine(engine, gt, id) {  in intel_engines_free()
719 		gt->engine[id] = NULL;  in intel_engines_free()
724 bool gen11_vdbox_has_sfc(struct intel_gt *gt,  in gen11_vdbox_has_sfc()  argument
728 	struct drm_i915_private *i915 = gt->i915;  in gen11_vdbox_has_sfc()
740 	if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)  in gen11_vdbox_has_sfc()
751 static void engine_mask_apply_media_fuses(struct intel_gt *gt)  in engine_mask_apply_media_fuses()  argument
753 	struct drm_i915_private *i915 = gt->i915;  in engine_mask_apply_media_fuses()
760 	if (MEDIA_VER(gt->i915) < 11)  in engine_mask_apply_media_fuses()
768 	media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);  in engine_mask_apply_media_fuses()
776 		fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);  in engine_mask_apply_media_fuses()
777 		gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);  in engine_mask_apply_media_fuses()
779 		gt->info.sfc_mask = ~0;  in engine_mask_apply_media_fuses()
783 		if (!HAS_ENGINE(gt, _VCS(i))) {  in engine_mask_apply_media_fuses()
789 			gt->info.engine_mask &= ~BIT(_VCS(i));  in engine_mask_apply_media_fuses()
790 			gt_dbg(gt, "vcs%u fused off\n", i);  in engine_mask_apply_media_fuses()
794 		if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))  in engine_mask_apply_media_fuses()
795 			gt->info.vdbox_sfc_access |= BIT(i);  in engine_mask_apply_media_fuses()
798 	gt_dbg(gt, "vdbox enable: %04x, instances: %04lx\n", vdbox_mask, VDBOX_MASK(gt));  in engine_mask_apply_media_fuses()
799 	GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));  in engine_mask_apply_media_fuses()
802 		if (!HAS_ENGINE(gt, _VECS(i))) {  in engine_mask_apply_media_fuses()
808 			gt->info.engine_mask &= ~BIT(_VECS(i));  in engine_mask_apply_media_fuses()
809 			gt_dbg(gt, "vecs%u fused off\n", i);  in engine_mask_apply_media_fuses()
812 	gt_dbg(gt, "vebox enable: %04x, instances: %04lx\n", vebox_mask, VEBOX_MASK(gt));  in engine_mask_apply_media_fuses()
813 	GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));  in engine_mask_apply_media_fuses()
816 static void engine_mask_apply_compute_fuses(struct intel_gt *gt)  in engine_mask_apply_compute_fuses()  argument
818 	struct drm_i915_private *i915 = gt->i915;  in engine_mask_apply_compute_fuses()
819 	struct intel_gt_info *info = &gt->info;  in engine_mask_apply_compute_fuses()
827 	if (hweight32(CCS_MASK(gt)) <= 1)  in engine_mask_apply_compute_fuses()
838 		gt_dbg(gt, "ccs%u fused off\n", i);  in engine_mask_apply_compute_fuses()
852 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)  in init_engine_mask()  argument
854 	struct intel_gt_info *info = &gt->info;  in init_engine_mask()
858 	engine_mask_apply_media_fuses(gt);  in init_engine_mask()
859 	engine_mask_apply_compute_fuses(gt);  in init_engine_mask()
873 	if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(&gt->uc)) {  in init_engine_mask()
874 		gt_notice(gt, "No GSC FW selected, disabling GSC CS and media C6\n");  in init_engine_mask()
886 	if (IS_DG2(gt->i915)) {  in init_engine_mask()
887 		u8 first_ccs = __ffs(CCS_MASK(gt));  in init_engine_mask()
893 		gt->ccs.cslices = CCS_MASK(gt);  in init_engine_mask()
904 static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids,  in populate_logical_ids()  argument
912 			if (!HAS_ENGINE(gt, i) ||  in populate_logical_ids()
925 static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class)  in setup_logical_ids()  argument
931 	if (MEDIA_VER(gt->i915) >= 11 && class == VIDEO_DECODE_CLASS) {  in setup_logical_ids()
934 		populate_logical_ids(gt, logical_ids, class,  in setup_logical_ids()
942 		populate_logical_ids(gt, logical_ids, class,  in setup_logical_ids()
953 int intel_engines_init_mmio(struct intel_gt *gt)  in intel_engines_init_mmio()  argument
955 	struct drm_i915_private *i915 = gt->i915;  in intel_engines_init_mmio()
956 	const unsigned int engine_mask = init_engine_mask(gt);  in intel_engines_init_mmio()
967 		setup_logical_ids(gt, logical_ids, class);  in intel_engines_init_mmio()
973 			    !HAS_ENGINE(gt, i))  in intel_engines_init_mmio()
976 			err = intel_engine_setup(gt, i,  in intel_engines_init_mmio()
991 		gt->info.engine_mask = mask;  in intel_engines_init_mmio()
993 	gt->info.num_engines = hweight32(mask);  in intel_engines_init_mmio()
995 	intel_gt_check_and_clear_faults(gt);  in intel_engines_init_mmio()
997 	intel_setup_engine_capabilities(gt);  in intel_engines_init_mmio()
999 	intel_uncore_prune_engine_fw_domains(gt->uncore, gt);  in intel_engines_init_mmio()
1004 	intel_engines_free(gt);  in intel_engines_init_mmio()
1046 	if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))  in pin_ggtt_status_page()
1084 		gt_err(engine->gt, "Failed to allocate status page\n");  in init_status_page()
1090 	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);  in init_status_page()
1175 	if (engine->gt->type == GT_MEDIA) {  in intel_engine_init_tlb_invalidation()
1199 	if (gt_WARN_ONCE(engine->gt, !num,  in intel_engine_init_tlb_invalidation()
1203 	if (gt_WARN_ON_ONCE(engine->gt,  in intel_engine_init_tlb_invalidation()
1280 		intel_sseu_from_device_info(&engine->gt->info.sseu);  in engine_setup_common()
1312 	GEM_BUG_ON(!engine->gt->scratch);  in measure_breadcrumb_dw()
1413 	return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K,  in create_ggtt_bind_context()
1423 	return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,  in create_kernel_context()
1489 int intel_engines_init(struct intel_gt *gt)  in intel_engines_init()  argument
1496 	if (intel_uc_uses_guc_submission(&gt->uc)) {  in intel_engines_init()
1497 		gt->submission_method = INTEL_SUBMISSION_GUC;  in intel_engines_init()
1499 	} else if (HAS_EXECLISTS(gt->i915)) {  in intel_engines_init()
1500 		gt->submission_method = INTEL_SUBMISSION_ELSP;  in intel_engines_init()
1503 		gt->submission_method = INTEL_SUBMISSION_RING;  in intel_engines_init()
1507 	for_each_engine(engine, gt, id) {  in intel_engines_init()
1637 	if (intel_engine_reset_needs_wa_22011802037(engine->gt))  in __intel_engine_stop_cs()
1731 static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)  in __gpm_wait_for_fw_complete()  argument
1739 	ret =  __intel_wait_for_register_fw(gt->uncore,  in __gpm_wait_for_fw_complete()
1747 		GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);  in __gpm_wait_for_fw_complete()
1764 		__gpm_wait_for_fw_complete(engine->gt, fw_pending);  in intel_engine_wait_for_pending_mi_fw()
1796 		for_each_ss_steering(iter, engine->gt, slice, subslice) {  in intel_engine_get_instdone()
1798 				intel_gt_mcr_read(engine->gt,  in intel_engine_get_instdone()
1802 				intel_gt_mcr_read(engine->gt,  in intel_engine_get_instdone()
1808 			for_each_ss_steering(iter, engine->gt, slice, subslice)  in intel_engine_get_instdone()
1810 					intel_gt_mcr_read(engine->gt,  in intel_engine_get_instdone()
1895 	if (intel_gt_is_wedged(engine->gt))  in intel_engine_is_idle()
1913 bool intel_engines_are_idle(struct intel_gt *gt)  in intel_engines_are_idle()  argument
1922 	if (intel_gt_is_wedged(gt))  in intel_engines_are_idle()
1926 	if (!READ_ONCE(gt->awake))  in intel_engines_are_idle()
1929 	for_each_engine(engine, gt, id) {  in intel_engines_are_idle()
1943 	spin_lock(engine->gt->irq_lock);  in intel_engine_irq_enable()
1945 	spin_unlock(engine->gt->irq_lock);  in intel_engine_irq_enable()
1956 	spin_lock(engine->gt->irq_lock);  in intel_engine_irq_disable()
1958 	spin_unlock(engine->gt->irq_lock);  in intel_engine_irq_disable()
1961 void intel_engines_reset_default_submission(struct intel_gt *gt)  in intel_engines_reset_default_submission()  argument
1966 	for_each_engine(engine, gt, id) {  in intel_engines_reset_default_submission()
2363 	if (intel_uc_uses_guc_submission(&engine->gt->uc))  in engine_dump_active_requests()
2389 	if (intel_gt_is_wedged(engine->gt))  in intel_engine_dump()
2471 	GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc));  in engine_execlist_find_hung_request()
2531 	if (intel_uc_uses_guc_submission(&engine->gt->uc))  in intel_engine_get_hung_entity()
2551 	if (!CCS_MASK(engine->gt))  in xehp_enable_ccs_engines()