| /linux/drivers/dpll/ |
| H A D | dpll_netlink.c | 16 #include <uapi/linux/dpll.h>
34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) in dpll_msg_add_dev_handle() argument
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, in dpll_pin_available()
99 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, in dpll_netdev_pin_handle_size()
102 const struct dpll_device_ops *ops = dpll_device_ops(dpll);
106 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_netdev_add_pin_handle()
116 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode()
119 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode()
110 dpll_msg_add_mode(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_mode() argument
127 dpll_msg_add_mode_supported(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_mode_supported() argument
159 dpll_msg_add_phase_offset_monitor(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_phase_offset_monitor() argument
179 dpll_msg_add_freq_monitor(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_freq_monitor() argument
200 dpll_msg_add_phase_offset_avg_factor(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_phase_offset_avg_factor() argument
220 dpll_msg_add_lock_status(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_lock_status() argument
244 dpll_msg_add_temp(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_temp() argument
263 dpll_msg_add_clock_quality_level(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_clock_quality_level() argument
289 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_prio() local
311 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_on_dpll_state() local
333 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_direction() local
353 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_phase_adjust() local
376 struct dpll_device *dpll = ref->dpll; dpll_msg_add_phase_offset() local
399 struct dpll_device *dpll = ref->dpll; dpll_msg_add_ffo() local
429 struct dpll_device *dpll = ref->dpll; dpll_msg_add_measured_freq() local
460 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_freq() local
501 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_esync() local
547 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_ref_sync() local
746 dpll_device_get_one(struct dpll_device * dpll,struct sk_buff * msg,struct netlink_ext_ack * extack) dpll_device_get_one() argument
790 dpll_device_event_send(enum dpll_cmd event,struct dpll_device * dpll) dpll_device_event_send() argument
820 dpll_device_create_ntf(struct dpll_device * dpll) dpll_device_create_ntf() argument
826 dpll_device_delete_ntf(struct dpll_device * dpll) dpll_device_delete_ntf() argument
840 __dpll_device_change_ntf(struct dpll_device * dpll) __dpll_device_change_ntf() argument
855 dpll_device_change_ntf(struct dpll_device * dpll) dpll_device_change_ntf() argument
948 dpll_mode_set(struct dpll_device * dpll,struct nlattr * a,struct netlink_ext_ack * extack) dpll_mode_set() argument
987 dpll_phase_offset_monitor_set(struct dpll_device * dpll,struct nlattr * a,struct netlink_ext_ack * extack) dpll_phase_offset_monitor_set() argument
1012 dpll_phase_offset_avg_factor_set(struct dpll_device * dpll,struct nlattr * a,struct netlink_ext_ack * extack) dpll_phase_offset_avg_factor_set() argument
1029 dpll_freq_monitor_set(struct dpll_device * dpll,struct nlattr * a,struct netlink_ext_ack * extack) dpll_freq_monitor_set() argument
1061 struct dpll_device *dpll; dpll_pin_freq_set() local
1126 struct dpll_device *dpll; dpll_pin_esync_set() local
1206 struct dpll_device *dpll; dpll_pin_ref_sync_state_set() local
1338 dpll_pin_state_set(struct dpll_device * dpll,struct dpll_pin * pin,enum dpll_pin_state state,struct netlink_ext_ack * extack) dpll_pin_state_set() argument
1366 dpll_pin_prio_set(struct dpll_device * dpll,struct dpll_pin * pin,u32 prio,struct netlink_ext_ack * extack) dpll_pin_prio_set() argument
1393 dpll_pin_direction_set(struct dpll_pin * pin,struct dpll_device * dpll,enum dpll_pin_direction direction,struct netlink_ext_ack * extack) dpll_pin_direction_set() argument
1427 struct dpll_device *dpll; dpll_pin_phase_adj_set() local
1506 struct dpll_device *dpll; dpll_pin_parent_device_set() local
1833 struct dpll_device *dpll_match = NULL, *dpll; dpll_device_find() local
1901 struct dpll_device *dpll; dpll_nl_device_id_get_doit() local
1933 struct dpll_device *dpll = info->user_ptr[0]; dpll_nl_device_get_doit() local
1959 dpll_set_from_nlattr(struct dpll_device * dpll,struct genl_info * info) dpll_set_from_nlattr() argument
1998 struct dpll_device *dpll = info->user_ptr[0]; dpll_nl_device_set_doit() local
2006 struct dpll_device *dpll; dpll_nl_device_get_dumpit() local
[all...] |
| H A D | Makefile | 6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
|
| H A D | dpll_netlink.h | 7 int dpll_device_create_ntf(struct dpll_device *dpll);
9 int dpll_device_delete_ntf(struct dpll_device *dpll);
|
| /linux/include/linux/ |
| H A D | dpll.h | 10 #include <uapi/linux/dpll.h>
25 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
27 int (*mode_set)(const struct dpll_device *dpll, void *dpll_priv,
29 int (*supported_modes_get)(const struct dpll_device *dpll,
32 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
36 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
38 int (*clock_quality_level_get)(const struct dpll_device *dpll,
42 int (*phase_offset_monitor_set)(const struct dpll_device *dpll,
46 int (*phase_offset_monitor_get)(const struct dpll_device *dpll,
50 int (*phase_offset_avg_factor_set)(const struct dpll_device *dpll,
201 struct dpll_device *dpll; global() member
[all...] |
| /linux/drivers/gpu/drm/gma500/ |
| H A D | psb_intel_display.c | 108 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
159 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
161 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
162 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
164 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
168 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
169 dpll |= in psb_intel_crtc_mode_set()
174 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
177 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
180 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
|
| H A D | cdv_intel_display.c | 585 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
666 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
677 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
723 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
724 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
759 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
768 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
769 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
770 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
774 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
[all …]
|
| H A D | gma_display.c | 223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
311 temp = REG_READ(map->dpll); in gma_crtc_dpms()
313 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
314 REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
|
| H A D | oaktrail_hdmi.c | 286 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
296 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
297 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
298 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
312 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
313 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
314 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
318 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
|
| H A D | oaktrail_device.c | 144 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers()
261 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers()
402 .dpll = MRST_DPLL_A,
426 .dpll = DPLL_B,
|
| H A D | psb_device.c | 204 .dpll = DPLL_A,
228 .dpll = DPLL_B,
|
| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | dpll.txt | 16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
23 "ti,omap4-dpll-m4xen-clock",
24 "ti,omap4-dpll-j-type-clock",
25 "ti,omap5-mpu-dpll-clock",
[all …]
|
| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_dpll.c | 8 #include <linux/dpll.h>
99 * for pin control. For E810 NIC with dpll there is additional MUX-related logic in ice_dpll_is_sw_pin()
100 * between SMA/U.FL pins/connectors and dpll device, best to give user access in ice_dpll_is_sw_pin()
196 * @dpll: pointer to dpll
197 * @dpll_priv: private data pointer passed on dpll registration
211 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_set()
235 * @dpll: pointer to dpll
236 * @dpll_priv: private data pointer passed on dpll registratio
202 ice_dpll_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,const u32 frequency,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type) ice_dpll_frequency_set() argument
240 ice_dpll_input_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) ice_dpll_input_frequency_set() argument
265 ice_dpll_output_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) ice_dpll_output_frequency_set() argument
291 ice_dpll_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type) ice_dpll_frequency_get() argument
324 ice_dpll_input_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) ice_dpll_input_frequency_get() argument
349 ice_dpll_output_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) ice_dpll_output_frequency_get() argument
374 ice_dpll_sw_pin_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) ice_dpll_sw_pin_frequency_set() argument
414 ice_dpll_sw_pin_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) ice_dpll_sw_pin_frequency_get() argument
812 ice_dpll_hw_input_prio_set(struct ice_pf * pf,struct ice_dpll * dpll,struct ice_dpll_pin * pin,const u32 prio,struct netlink_ext_ack * extack) ice_dpll_hw_input_prio_set() argument
848 ice_dpll_lock_status_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack) ice_dpll_lock_status_get() argument
877 ice_dpll_mode_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_mode * mode,struct netlink_ext_ack * extack) ice_dpll_mode_get() argument
903 ice_dpll_phase_offset_monitor_set(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state state,struct netlink_ext_ack * extack) ice_dpll_phase_offset_monitor_set() argument
934 ice_dpll_phase_offset_monitor_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state * state,struct netlink_ext_ack * extack) ice_dpll_phase_offset_monitor_get() argument
971 ice_dpll_pin_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,bool enable,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type) ice_dpll_pin_state_set() argument
1014 ice_dpll_output_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) ice_dpll_output_state_set() argument
1049 ice_dpll_input_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) ice_dpll_input_state_set() argument
1078 ice_dpll_pin_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type) ice_dpll_pin_state_get() argument
1123 ice_dpll_output_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) ice_dpll_output_state_get() argument
1149 ice_dpll_input_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) ice_dpll_input_state_get() argument
1284 ice_dpll_ufl_pin_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) ice_dpll_ufl_pin_state_set() argument
1397 ice_dpll_sw_pin_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) ice_dpll_sw_pin_state_get() argument
1453 ice_dpll_sma_pin_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) ice_dpll_sma_pin_state_set() argument
1517 ice_dpll_input_prio_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 * prio,struct netlink_ext_ack * extack) ice_dpll_input_prio_get() argument
1549 ice_dpll_input_prio_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 prio,struct netlink_ext_ack * extack) ice_dpll_input_prio_set() argument
1569 ice_dpll_sw_input_prio_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 * prio,struct netlink_ext_ack * extack) ice_dpll_sw_input_prio_get() argument
1588 ice_dpll_sw_input_prio_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 prio,struct netlink_ext_ack * extack) ice_dpll_sw_input_prio_set() argument
1624 ice_dpll_input_direction(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack) ice_dpll_input_direction() argument
1649 ice_dpll_output_direction(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack) ice_dpll_output_direction() argument
1676 ice_dpll_pin_sma_direction_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction direction,struct netlink_ext_ack * extack) ice_dpll_pin_sma_direction_set() argument
1714 ice_dpll_pin_sw_direction_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack) ice_dpll_pin_sw_direction_get() argument
1748 ice_dpll_pin_phase_adjust_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack) ice_dpll_pin_phase_adjust_get() argument
1782 ice_dpll_pin_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack,enum ice_dpll_pin_type type) ice_dpll_pin_phase_adjust_set() argument
1851 ice_dpll_input_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) ice_dpll_input_phase_adjust_set() argument
1879 ice_dpll_output_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) ice_dpll_output_phase_adjust_set() argument
1907 ice_dpll_sw_phase_adjust_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack) ice_dpll_sw_phase_adjust_get() argument
1942 ice_dpll_sw_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) ice_dpll_sw_phase_adjust_set() argument
1986 ice_dpll_phase_offset_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s64 * phase_offset,struct netlink_ext_ack * extack) ice_dpll_phase_offset_get() argument
2062 ice_dpll_output_esync_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) ice_dpll_output_esync_set() argument
2117 ice_dpll_output_esync_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) ice_dpll_output_esync_get() argument
2166 ice_dpll_input_esync_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) ice_dpll_input_esync_set() argument
2221 ice_dpll_input_esync_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) ice_dpll_input_esync_get() argument
2270 ice_dpll_sw_esync_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) ice_dpll_sw_esync_set() argument
2306 ice_dpll_sw_esync_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) ice_dpll_sw_esync_get() argument
3131 ice_dpll_unregister_pins(struct dpll_device * dpll,struct ice_dpll_pin * pins,const struct dpll_pin_ops * ops,int count) ice_dpll_unregister_pins() argument
3185 ice_dpll_register_pins(struct dpll_device * dpll,struct ice_dpll_pin * pins,const struct dpll_pin_ops * ops,int count) ice_dpll_register_pins() argument
[all...] |
| /linux/drivers/net/ethernet/mellanox/mlx5/core/ |
| H A D | dpll.c | 4 #include <linux/dpll.h>
11 struct dpll_device *dpll; member
146 mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, void *priv, in mlx5_dpll_device_lock_status_get() argument
163 static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll, in mlx5_dpll_device_mode_get() argument
200 static int mlx5_dpll_clock_quality_level_get(const struct dpll_device *dpll, in mlx5_dpll_clock_quality_level_get() argument
259 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument
270 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument
288 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument
302 const struct dpll_device *dpll, void *dpll_priv, in mlx5_dpll_ffo_get() argument
356 dpll_device_change_ntf(mdpll->dpll); in mlx5_dpll_periodic_work()
[all...] |
| /linux/drivers/dpll/zl3073x/ |
| H A D | dpll.c | 9 #include <linux/dpll.h>
22 #include "dpll.h"
32 * @dpll: DPLL the pin is registered to
49 struct zl3073x_dpll *dpll;
98 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_pin_direction_get()
126 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_get()
163 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_set()
203 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_input_pin_ref_sync_get()
232 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_input_pin_ref_sync_set()
298 const struct dpll_device *dpll, voi in zl3073x_dpll_input_pin_ffo_get()
48 struct zl3073x_dpll *dpll; global() member
97 zl3073x_dpll_pin_direction_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack) zl3073x_dpll_pin_direction_get() argument
125 zl3073x_dpll_input_pin_esync_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_esync_get() argument
162 zl3073x_dpll_input_pin_esync_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_esync_set() argument
297 zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s64 * ffo,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_ffo_get() argument
310 zl3073x_dpll_input_pin_measured_freq_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * measured_freq,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_measured_freq_get() argument
325 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_frequency_get() argument
342 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_frequency_set() argument
389 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s64 * phase_offset,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_phase_offset_get() argument
445 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_phase_adjust_get() argument
478 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_phase_adjust_set() argument
550 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_state_on_dpll_get() argument
563 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_state_on_dpll_set() argument
649 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 * prio,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_prio_get() argument
661 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 prio,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_prio_set() argument
692 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_esync_get() argument
750 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_esync_set() argument
807 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_frequency_get() argument
822 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_frequency_set() argument
896 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_phase_adjust_get() argument
919 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_phase_adjust_set() argument
943 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_state_on_dpll_get() argument
955 zl3073x_dpll_temp_get(const struct dpll_device * dpll,void * dpll_priv,s32 * temp,struct netlink_ext_ack * extack) zl3073x_dpll_temp_get() argument
974 zl3073x_dpll_lock_status_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack) zl3073x_dpll_lock_status_get() argument
1018 zl3073x_dpll_supported_modes_get(const struct dpll_device * dpll,void * dpll_priv,unsigned long * modes,struct netlink_ext_ack * extack) zl3073x_dpll_supported_modes_get() argument
1041 zl3073x_dpll_mode_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_mode * mode,struct netlink_ext_ack * extack) zl3073x_dpll_mode_get() argument
1071 zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device * dpll,void * dpll_priv,u32 * factor,struct netlink_ext_ack * extack) zl3073x_dpll_phase_offset_avg_factor_get() argument
1083 zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device * dpll,void * dpll_priv,u32 factor,struct netlink_ext_ack * extack) zl3073x_dpll_phase_offset_avg_factor_set() argument
1117 zl3073x_dpll_mode_set(const struct dpll_device * dpll,void * dpll_priv,enum dpll_mode mode,struct netlink_ext_ack * extack) zl3073x_dpll_mode_set() argument
1179 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_phase_offset_monitor_get() argument
1195 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state state,struct netlink_ext_ack * extack) zl3073x_dpll_phase_offset_monitor_set() argument
1208 zl3073x_dpll_freq_monitor_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_freq_monitor_get() argument
1224 zl3073x_dpll_freq_monitor_set(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state state,struct netlink_ext_ack * extack) zl3073x_dpll_freq_monitor_set() argument
[all...] |
| /linux/arch/arm/mach-omap1/ |
| H A D | sram.S | 36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
|
| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | am43xx-clocks.dtsi | 231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
[all …]
|
| H A D | am33xx-clocks.dtsi | 191 compatible = "ti,am3-dpll-core-clock";
197 dpll_core_x2_ck: clock-dpll-core-x2 {
199 compatible = "ti,am3-dpll-x2-clock";
204 dpll_core_m4_ck: clock-dpll-core-m4@480 {
214 dpll_core_m5_ck: clock-dpll-core-m5@484 {
224 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
236 compatible = "ti,am3-dpll-clock";
242 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
254 compatible = "ti,am3-dpll-no-gate-clock";
260 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
[all …]
|
| H A D | omap54xx-clocks.dtsi | 119 compatible = "ti,omap4-dpll-m4xen-clock";
127 compatible = "ti,omap4-dpll-x2-clock";
201 compatible = "ti,omap4-dpll-core-clock";
209 compatible = "ti,omap4-dpll-x2-clock";
352 compatible = "ti,omap4-dpll-clock";
362 compatible = "ti,omap4-dpll-x2-clock";
402 compatible = "ti,omap5-mpu-dpll-clock";
586 compatible = "ti,omap4-dpll-clock";
594 compatible = "ti,omap4-dpll-x2-clock";
661 compatible = "ti,omap4-dpll-clock";
[all …]
|
| H A D | omap44xx-clocks.dtsi | 154 compatible = "ti,omap4-dpll-m4xen-clock";
162 compatible = "ti,omap4-dpll-x2-clock";
223 compatible = "ti,omap4-dpll-core-clock";
231 compatible = "ti,omap4-dpll-x2-clock";
390 compatible = "ti,omap4-dpll-clock";
400 compatible = "ti,omap4-dpll-x2-clock";
435 compatible = "ti,omap4-dpll-clock";
636 compatible = "ti,omap4-dpll-clock";
654 compatible = "ti,omap4-dpll-x2-clock";
748 compatible = "ti,omap4-dpll-j-type-clock";
|
| /linux/drivers/ata/ |
| H A D | pata_hpt3x2n.c | 312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
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| H A D | pata_hpt37x.c | 948 int dpll, adjust; in hpt37x_init_one() local
951 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
953 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
981 if (dpll == 3) in hpt37x_init_one()
987 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
|
| /linux/drivers/gpu/drm/renesas/rcar-du/ |
| H A D | rcar_du_crtc.c | 84 struct dpll_info *dpll, in rcar_du_dpll_divider() argument
148 dpll->n = n; in rcar_du_dpll_divider()
149 dpll->m = m; in rcar_du_dpll_divider()
150 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
151 dpll->output = output; in rcar_du_dpll_divider()
163 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
218 struct dpll_info dpll in rcar_du_crtc_set_display_timing() local
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| /linux/arch/arm64/boot/dts/sprd/ |
| H A D | sharkl3.dtsi | 123 dpll: dpll@0 { label
124 compatible = "sprd,sc9863a-dpll";
|
| /linux/drivers/gpu/drm/i915/display/ |
| H A D | g4x_dp.c | 34 static const struct dpll g4x_dpll[] = {
39 static const struct dpll pch_dpll[] = {
44 static const struct dpll vlv_dpll[] = {
49 static const struct dpll chv_dpll[] = {
55 const struct dpll *vlv_get_dpll(struct intel_display *display) in vlv_get_dpll()
64 const struct dpll *divisor = NULL; in g4x_dp_set_clock()
84 pipe_config->dpll = divisor[i]; in g4x_dp_set_clock()
|
| H A D | intel_dvo.c | 407 u32 dpll[I915_MAX_PIPES]; in intel_dvo_connector_type()
446 dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0, in intel_dvo_init_dev()
453 intel_de_write(display, DPLL(display, pipe), dpll[pipe]); in intel_dvo_init_dev()
422 u32 dpll[I915_MAX_PIPES]; intel_dvo_init_dev() local
|