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Searched refs:cr4 (Results 1 – 25 of 39) sorted by relevance

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/linux/tools/testing/selftests/kvm/x86/
H A Dset_sregs_test.c53 u64 cr4 = KVM_ALWAYS_ALLOWED_CR4; in calc_supported_cr4_feature_bits()
56 cr4 |= X86_CR4_UMIP; in calc_supported_cr4_feature_bits()
58 cr4 |= X86_CR4_LA57; in calc_supported_cr4_feature_bits()
60 cr4 |= X86_CR4_VMXE; in calc_supported_cr4_feature_bits()
62 cr4 |= X86_CR4_SMXE; in calc_supported_cr4_feature_bits()
64 cr4 |= X86_CR4_FSGSBASE; in calc_supported_cr4_feature_bits()
66 cr4 |= X86_CR4_PCIDE; in calc_supported_cr4_feature_bits()
68 cr4 |= X86_CR4_OSXSAVE; in calc_supported_cr4_feature_bits()
70 cr4 |= X86_CR4_SMEP; in calc_supported_cr4_feature_bits()
72 cr4 | in calc_supported_cr4_feature_bits()
51 u64 cr4 = KVM_ALWAYS_ALLOWED_CR4; calc_supported_cr4_feature_bits() local
77 test_cr_bits(struct kvm_vcpu * vcpu,u64 cr4) test_cr_bits() argument
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H A Dsync_regs_test.c138 __u64 *cr4 = &run->s.regs.sregs.cr4; in race_sregs_cr4() local
139 __u64 pae_enabled = *cr4; in race_sregs_cr4()
140 __u64 pae_disabled = *cr4 & ~X86_CR4_PAE; in race_sregs_cr4()
144 WRITE_ONCE(*cr4, pae_enabled); in race_sregs_cr4()
148 WRITE_ONCE(*cr4, pae_disabled); in race_sregs_cr4()
178 TEST_ASSERT((run->s.regs.sregs.cr4 & X86_CR4_PAE) && in race_sync_regs()
181 !!(run->s.regs.sregs.cr4 & X86_CR4_PAE), in race_sync_regs()
H A Dcpuid_test.c172 sregs.cr4 ^= X86_CR4_OSXSAVE; in set_cpuid_after_run()
174 sregs.cr4 ^= X86_CR4_PKE; in set_cpuid_after_run()
/linux/arch/x86/kernel/
H A Dsev_verify_cbit.S35 movq %cr4, %rsi
40 movq %rdx, %cr4
71 movq %rsi, %cr4
H A Drelocate_kernel_64.S96 movq %cr4, %r13
104 movq %r12, %cr4
176 movq %cr4, %rax
178 movq %rax, %cr4
206 movq %r13, %cr4
314 movq %rax, %cr4
H A Dhead_64.S222 movq %cr4, %rcx
227 movq %rcx, %cr4
233 movq %rcx, %cr4
H A Dhead64.c274 __native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4)); in x86_64_start_kernel()
/linux/arch/x86/kernel/cpu/mtrr/
H A Dcyrix.c135 static u32 cr4, ccr3; variable
143 cr4 = __read_cr4(); in prepare_set()
144 __write_cr4(cr4 & ~X86_CR4_PGE); in prepare_set()
176 __write_cr4(cr4); in post_set()
/linux/arch/x86/power/
H A Dhibernate_asm_64.S37 movq %rdx, %cr4; # turn off PGE
40 movq %rax, %cr4; # turn PGE back on
129 movq %rcx, %cr4; # turn off PGE
132 movq %rbx, %cr4; # turn PGE back on
H A Dcpu.c128 ctxt->cr4 = __read_cr4(); in __save_processor_state()
208 if (ctxt->cr4) in __restore_processor_state()
209 __write_cr4(ctxt->cr4); in __restore_processor_state()
213 __write_cr4(ctxt->cr4); in __restore_processor_state()
245 if (ctxt->cr4 & X86_CR4_FRED) { in __restore_processor_state()
/linux/arch/x86/mm/
H A Dmem_encrypt_boot.S103 mov %cr4, %rdx
105 mov %rdx, %cr4
107 mov %rdx, %cr4
/linux/tools/testing/selftests/kvm/lib/x86/
H A Dvmx.c133 unsigned long cr4; in prepare_for_vmx_operation()
145 __asm__ __volatile__("mov %%cr4, %0" : "=r"(cr4) : : "memory"); in prepare_for_vmx_operation()
146 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); in prepare_for_vmx_operation()
147 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); in prepare_for_vmx_operation()
149 cr4 |= X86_CR4_VMXE; in prepare_for_vmx_operation()
150 __asm__ __volatile__("mov %0, %%cr4" : : "r"(cr4) : "memory"); in prepare_for_vmx_operation()
131 unsigned long cr4; prepare_for_vmx_operation() local
H A Dsvm.c111 asm volatile ("mov %%cr4, %0" : "=r"(save->cr4) : : "memory"); in generic_svm_setup()
/linux/include/xen/interface/hvm/
H A Dhvm_vcpu.h25 uint32_t cr4; member
88 uint64_t cr4; member
/linux/arch/x86/platform/olpc/
H A Dxo1-wakeup.S30 movl %eax, %cr4
64 movl %cr4, %edx
/linux/arch/x86/kvm/
H A Dsmm.h31 u32 cr4; member
127 u64 cr4; member
/linux/arch/powerpc/kernel/
H A Dcpu_setup_6xx.S366 cmplwi cr4,r3,0x8002 /* 7457 */
374 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
437 cmplwi cr4,r3,0x8002 /* 7457 */
445 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
/linux/scripts/gdb/linux/
H A Dpgtable.py209 cr4 = gdb.parse_and_eval('$cr4')
210 page_levels = 5 if cr4 & (1 << 12) else 4
/linux/arch/x86/hyperv/
H A Dhv_crash.c61 ulong cr4; member
171 asm volatile("movq %0, %%cr4" : : "r"(hv_crash_ctxt.cr4)); in hv_crash_c_entry()
205 ctxt->cr4 = native_read_cr4(); in hv_hvcrash_ctxt_save()
H A Dhv_trampoline.S49 movl %ecx, %cr4
/linux/arch/x86/realmode/rm/
H A Dtrampoline_64.S157 movl %eax, %cr4 # Enable PAE mode
226 movq %cr4, %rax
H A Dwakeup_asm.S117 movl %eax, %cr4
/linux/arch/x86/include/asm/
H A Drealmode.h53 u32 cr4;
/linux/arch/powerpc/boot/
H A Dppc_asm.h17 #define cr4 4 macro
/linux/arch/x86/kvm/vmx/
H A Dvmx.c2672 vcpu->arch.cr4 &= ~guest_owned_bits; in vmx_cache_reg()
2673 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits; in vmx_cache_reg()
3568 bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) in vmx_is_valid_cr4() argument
3575 if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu)) in vmx_is_valid_cr4()
3578 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) in vmx_is_valid_cr4()
3584 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) in vmx_set_cr4() argument
3595 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); in vmx_set_cr4()
3604 if (cr4 & X86_CR4_UMIP) { in vmx_set_cr4()
3613 vcpu->arch.cr4 = cr4; in vmx_set_cr4()
3621 } else if (!(cr4 & X86_CR4_PAE)) { in vmx_set_cr4()
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