1*9e2b3e83SJuergen Gross /* SPDX-License-Identifier: MIT */ 2cee2cfb7SBoris Ostrovsky /* 3cee2cfb7SBoris Ostrovsky * Copyright (c) 2015, Roger Pau Monne <roger.pau@citrix.com> 4cee2cfb7SBoris Ostrovsky */ 5cee2cfb7SBoris Ostrovsky 6cee2cfb7SBoris Ostrovsky #ifndef __XEN_PUBLIC_HVM_HVM_VCPU_H__ 7cee2cfb7SBoris Ostrovsky #define __XEN_PUBLIC_HVM_HVM_VCPU_H__ 8cee2cfb7SBoris Ostrovsky 9cee2cfb7SBoris Ostrovsky #include "../xen.h" 10cee2cfb7SBoris Ostrovsky 11cee2cfb7SBoris Ostrovsky struct vcpu_hvm_x86_32 { 12cee2cfb7SBoris Ostrovsky uint32_t eax; 13cee2cfb7SBoris Ostrovsky uint32_t ecx; 14cee2cfb7SBoris Ostrovsky uint32_t edx; 15cee2cfb7SBoris Ostrovsky uint32_t ebx; 16cee2cfb7SBoris Ostrovsky uint32_t esp; 17cee2cfb7SBoris Ostrovsky uint32_t ebp; 18cee2cfb7SBoris Ostrovsky uint32_t esi; 19cee2cfb7SBoris Ostrovsky uint32_t edi; 20cee2cfb7SBoris Ostrovsky uint32_t eip; 21cee2cfb7SBoris Ostrovsky uint32_t eflags; 22cee2cfb7SBoris Ostrovsky 23cee2cfb7SBoris Ostrovsky uint32_t cr0; 24cee2cfb7SBoris Ostrovsky uint32_t cr3; 25cee2cfb7SBoris Ostrovsky uint32_t cr4; 26cee2cfb7SBoris Ostrovsky 27cee2cfb7SBoris Ostrovsky uint32_t pad1; 28cee2cfb7SBoris Ostrovsky 29cee2cfb7SBoris Ostrovsky /* 30cee2cfb7SBoris Ostrovsky * EFER should only be used to set the NXE bit (if required) 31cee2cfb7SBoris Ostrovsky * when starting a vCPU in 32bit mode with paging enabled or 32cee2cfb7SBoris Ostrovsky * to set the LME/LMA bits in order to start the vCPU in 33cee2cfb7SBoris Ostrovsky * compatibility mode. 34cee2cfb7SBoris Ostrovsky */ 35cee2cfb7SBoris Ostrovsky uint64_t efer; 36cee2cfb7SBoris Ostrovsky 37cee2cfb7SBoris Ostrovsky uint32_t cs_base; 38cee2cfb7SBoris Ostrovsky uint32_t ds_base; 39cee2cfb7SBoris Ostrovsky uint32_t ss_base; 40cee2cfb7SBoris Ostrovsky uint32_t es_base; 41cee2cfb7SBoris Ostrovsky uint32_t tr_base; 42cee2cfb7SBoris Ostrovsky uint32_t cs_limit; 43cee2cfb7SBoris Ostrovsky uint32_t ds_limit; 44cee2cfb7SBoris Ostrovsky uint32_t ss_limit; 45cee2cfb7SBoris Ostrovsky uint32_t es_limit; 46cee2cfb7SBoris Ostrovsky uint32_t tr_limit; 47cee2cfb7SBoris Ostrovsky uint16_t cs_ar; 48cee2cfb7SBoris Ostrovsky uint16_t ds_ar; 49cee2cfb7SBoris Ostrovsky uint16_t ss_ar; 50cee2cfb7SBoris Ostrovsky uint16_t es_ar; 51cee2cfb7SBoris Ostrovsky uint16_t tr_ar; 52cee2cfb7SBoris Ostrovsky 53cee2cfb7SBoris Ostrovsky uint16_t pad2[3]; 54cee2cfb7SBoris Ostrovsky }; 55cee2cfb7SBoris Ostrovsky 56cee2cfb7SBoris Ostrovsky /* 57cee2cfb7SBoris Ostrovsky * The layout of the _ar fields of the segment registers is the 58cee2cfb7SBoris Ostrovsky * following: 59cee2cfb7SBoris Ostrovsky * 60cee2cfb7SBoris Ostrovsky * Bits [0,3]: type (bits 40-43). 61cee2cfb7SBoris Ostrovsky * Bit 4: s (descriptor type, bit 44). 62cee2cfb7SBoris Ostrovsky * Bit [5,6]: dpl (descriptor privilege level, bits 45-46). 63cee2cfb7SBoris Ostrovsky * Bit 7: p (segment-present, bit 47). 64cee2cfb7SBoris Ostrovsky * Bit 8: avl (available for system software, bit 52). 65cee2cfb7SBoris Ostrovsky * Bit 9: l (64-bit code segment, bit 53). 66cee2cfb7SBoris Ostrovsky * Bit 10: db (meaning depends on the segment, bit 54). 67cee2cfb7SBoris Ostrovsky * Bit 11: g (granularity, bit 55) 68cee2cfb7SBoris Ostrovsky * Bits [12,15]: unused, must be blank. 69cee2cfb7SBoris Ostrovsky * 70cee2cfb7SBoris Ostrovsky * A more complete description of the meaning of this fields can be 71cee2cfb7SBoris Ostrovsky * obtained from the Intel SDM, Volume 3, section 3.4.5. 72cee2cfb7SBoris Ostrovsky */ 73cee2cfb7SBoris Ostrovsky 74cee2cfb7SBoris Ostrovsky struct vcpu_hvm_x86_64 { 75cee2cfb7SBoris Ostrovsky uint64_t rax; 76cee2cfb7SBoris Ostrovsky uint64_t rcx; 77cee2cfb7SBoris Ostrovsky uint64_t rdx; 78cee2cfb7SBoris Ostrovsky uint64_t rbx; 79cee2cfb7SBoris Ostrovsky uint64_t rsp; 80cee2cfb7SBoris Ostrovsky uint64_t rbp; 81cee2cfb7SBoris Ostrovsky uint64_t rsi; 82cee2cfb7SBoris Ostrovsky uint64_t rdi; 83cee2cfb7SBoris Ostrovsky uint64_t rip; 84cee2cfb7SBoris Ostrovsky uint64_t rflags; 85cee2cfb7SBoris Ostrovsky 86cee2cfb7SBoris Ostrovsky uint64_t cr0; 87cee2cfb7SBoris Ostrovsky uint64_t cr3; 88cee2cfb7SBoris Ostrovsky uint64_t cr4; 89cee2cfb7SBoris Ostrovsky uint64_t efer; 90cee2cfb7SBoris Ostrovsky 91cee2cfb7SBoris Ostrovsky /* 92cee2cfb7SBoris Ostrovsky * Using VCPU_HVM_MODE_64B implies that the vCPU is launched 93cee2cfb7SBoris Ostrovsky * directly in long mode, so the cached parts of the segment 94cee2cfb7SBoris Ostrovsky * registers get set to match that environment. 95cee2cfb7SBoris Ostrovsky * 96cee2cfb7SBoris Ostrovsky * If the user wants to launch the vCPU in compatibility mode 97cee2cfb7SBoris Ostrovsky * the 32-bit structure should be used instead. 98cee2cfb7SBoris Ostrovsky */ 99cee2cfb7SBoris Ostrovsky }; 100cee2cfb7SBoris Ostrovsky 101cee2cfb7SBoris Ostrovsky struct vcpu_hvm_context { 102cee2cfb7SBoris Ostrovsky #define VCPU_HVM_MODE_32B 0 /* 32bit fields of the structure will be used. */ 103cee2cfb7SBoris Ostrovsky #define VCPU_HVM_MODE_64B 1 /* 64bit fields of the structure will be used. */ 104cee2cfb7SBoris Ostrovsky uint32_t mode; 105cee2cfb7SBoris Ostrovsky 106cee2cfb7SBoris Ostrovsky uint32_t pad; 107cee2cfb7SBoris Ostrovsky 108cee2cfb7SBoris Ostrovsky /* CPU registers. */ 109cee2cfb7SBoris Ostrovsky union { 110cee2cfb7SBoris Ostrovsky struct vcpu_hvm_x86_32 x86_32; 111cee2cfb7SBoris Ostrovsky struct vcpu_hvm_x86_64 x86_64; 112cee2cfb7SBoris Ostrovsky } cpu_regs; 113cee2cfb7SBoris Ostrovsky }; 114cee2cfb7SBoris Ostrovsky typedef struct vcpu_hvm_context vcpu_hvm_context_t; 115cee2cfb7SBoris Ostrovsky 116cee2cfb7SBoris Ostrovsky #endif /* __XEN_PUBLIC_HVM_HVM_VCPU_H__ */ 117