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Searched refs:PCS (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/net/phy/
H A Dqt2025.rs61 dev.write(C45::new(Mmd::PCS, 0x0026), 0x0e00)?; in probe()
62 dev.write(C45::new(Mmd::PCS, 0x0027), 0x0893)?; in probe()
63 dev.write(C45::new(Mmd::PCS, 0x0028), 0xa528)?; in probe()
64 dev.write(C45::new(Mmd::PCS, 0x0029), 0x0003)?; in probe()
70 dev.write(C45::new(Mmd::PCS, 0xe854), 0x00c0)?; in probe()
81 let mut dst_mmd = Mmd::PCS; in probe()
94 dev.write(C45::new(Mmd::PCS, 0xe854), 0x0040)?; in probe()
/linux/drivers/net/pcs/
H A DKconfig3 # PCS Layer Configuration
6 menu "PCS device drivers"
18 This module provides helpers to phylink for managing the Lynx PCS
25 This module provides helpers to phylink for managing the LynxI PCS
33 on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
/linux/Documentation/networking/
H A Dsfp-phylink.rst219 should be used to configure the MAC when the MAC and PCS are not
249 10. Some Ethernet controllers work in pair with a PCS (Physical Coding Sublayer)
252 PCS whose operation is transparent, some other require dedicated PCS
254 provides a PCS abstraction through :c:type:`struct phylink_pcs <phylink_pcs>`.
256 Identify if your driver has one or more internal PCS blocks, and/or if
257 your controller can use an external PCS block that might be internally
260 If your controller doesn't have any internal PCS, you can go to step 11.
262 If your Ethernet controller contains one or several PCS blocks, create
263 one :c:type:`struct phylink_pcs <phylink_pcs>` instance per PCS block within
271 configure your PCS. Create a :c:func:`pcs_get_state` function that reports
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H A Dphy.rst301 This is the IEEE 802.3 PCS Clause 107 defined 25GBASE-R protocol.
302 The PCS is identical to 10GBASE-R, i.e. 64B/66B encoded
334 through symbol replication. The PCS expects the standard USXGMII code word.
H A Dethtool-netlink.rst1498 are counters corresponding to lanes/PCS instances. The number of entries in
/linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
H A Dmac-phy-support.rst54 | MC firmware polling MAC PCS for link |
56 | | PCS | | PCS | | PCS | | PCS | |
65 the MC firmware by polling the MAC PCS. Without the need to register a
187 mode, the MC firmware does not access the PCS registers). One can check for
/linux/Documentation/devicetree/bindings/net/
H A Damd-xgbe.txt7 - PCS registers
15 The last interrupt listed should be the PCS auto-negotiation interrupt.
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tsn.dts236 /* SGMII PCS for enet0 */
244 /* SGMII PCS for enet1 */
/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt13 set PCS delay value.
59 register offset to write the PCS delay value.
/linux/rust/kernel/net/phy/
H A Dreg.rs147 pub const PCS: Self = Mmd(uapi::MDIO_MMD_PCS as u8); constant
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Den_port.h331 __be64 PCS; member
H A Den_port.c310 stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) + in mlx4_en_DUMP_ETH_STATS()
/linux/sound/pci/
H A DKconfig605 FM801 chip with a TEA5757 tuner (MediaForte SF256-PCS, SF256-PCP and
/linux/Documentation/sound/
H A Dalsa-configuration.rst909 1 = MediaForte 256-PCS,
/linux/
H A DMAINTAINERS13670 LYNX PCS MODULE
14575 MEDIATEK ETHERNET PCS DRIVER