Searched refs:CPM (Results 1 – 12 of 12) sorted by relevance
1 PPC4xx Clock Power Management (CPM) node9 - er-offset : All 4xx SoCs with a CPM controller have10 one of two different order for the CPM11 registers. Some have the CPM registers18 in CPM will be set to turn off unused22 in CPM will be set to turn off unused23 devices. This is usually just CPM[CPU].26 in CPM will be set on standby and30 in CPM will be set on suspend (mem) and
7 * Root CPM node22 * Properties common to multiple CPM/QE devices25 to specify the device on which a CPM command operates.38 The multi-user/dual-ported RAM is expressed as a bus under the CPM node.47 CPM-side offsets with pointer subtraction. It is recommended that
37 …| CPM (core) | 0 | 0 | Snoop-Logic | CPM # …39 …| CPM (core) | 0 | 2 | Armv8 Core 1 | CPM # …
24 QE and two options for CPM.
18 CPM UART driver, the port-number is required for the QE UART driver.
3 The I2C controller is expressed as a bus under the CPM node.
4 select CPM94 menu "MPC8xx CPM Options"
234 bool "Early serial debugging for Freescale CPM-based serial ports"238 using a CPM-based serial port. This assumes that the bootwrapper239 has run, and set up the CPM in a particular way.338 hex "CPM UART early debug transmit descriptor address"
65 /* CON15,16 - CPM lane 4 */245 /* CPM Lane 5 - U29 */
145 * SPI on CPM and NAND have common pins on this board. We can
84 CPM, enumerator635 .version = CPM,
10430 FREESCALE I2C CPM DRIVER20998 PCI DRIVER FOR XILINX VERSAL CPM