| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 403 bool isSub = Opc == sub; variable
404 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
434 bool isSub = Opc == sub; variable
435 return ((int)isSub << 8) | Offset | (IdxMode << 9);
477 bool isSub = Opc == sub; in getAM5Opc() local
478 return ((int)isSub << 8) | Offset; in getAM5Opc()
498 bool isSub = Opc == sub; in getAM5FP16Opc() local
499 return ((int)isSub << 8) | Offset; in getAM5FP16Opc()
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| H A D | ARMInstPrinter.cpp | 406 bool isSub = OffImm < 0; in printThumbLdrLabelOperand() local
411 if (isSub) { in printThumbLdrLabelOperand()
1235 bool isSub = OffImm < 0; in printAddrModeImm12Operand() local
1239 if (isSub) { in printAddrModeImm12Operand()
1262 bool isSub = OffImm < 0; in printT2AddrModeImm8Operand() local
1266 if (isSub) { in printT2AddrModeImm8Operand()
1294 bool isSub = OffImm < 0; in printT2AddrModeImm8s4Operand() local
1301 if (isSub) { in printT2AddrModeImm8s4Operand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 325 bool isSub = NumBytes < 0; in emitT2RegPlusImmediate() local
326 if (isSub) NumBytes = -NumBytes; in emitT2RegPlusImmediate()
350 if (isSub) { in emitT2RegPlusImmediate()
393 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitT2RegPlusImmediate()
408 Opc = isSub ? t2SUB : t2ADD; in emitT2RegPlusImmediate()
415 Opc = isSub ? t2SUBi12 : t2ADDi12; in emitT2RegPlusImmediate()
561 bool isSub = false; in rewriteT2FrameIndex() local
593 isSub = true; in rewriteT2FrameIndex()
612 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex()
670 isSub = true; in rewriteT2FrameIndex()
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| H A D | ThumbRegisterInfo.cpp | 144 bool isSub = false; in emitThumbRegPlusImmInReg() local
150 isSub = true; in emitThumbRegPlusImmInReg()
233 int Opc = (isSub) ? ARM::tSUBrr in emitThumbRegPlusImmInReg()
238 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
256 bool isSub = NumBytes < 0; in emitThumbRegPlusImmediate() local
258 if (isSub) Bytes = -NumBytes; in emitThumbRegPlusImmediate()
291 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate()
297 assert(!isSub && "Thumb1 does not have tSUBrSPi"); in emitThumbRegPlusImmediate()
306 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3; in emitThumbRegPlusImmediate()
314 ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8; in emitThumbRegPlusImmediate()
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| H A D | ARMBaseInstrInfo.cpp | 2327 bool isSub = NumBytes < 0; in emitARMRegPlusImmediate() local
2328 if (isSub) NumBytes = -NumBytes; in emitARMRegPlusImmediate()
2341 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
2480 bool isSub = false; in rewriteARMFrameIndex() local
2497 isSub = true; in rewriteARMFrameIndex()
2584 isSub = true; in rewriteARMFrameIndex()
2599 if (isSub) { in rewriteARMFrameIndex()
2612 if (isSub) { in rewriteARMFrameIndex()
2623 Offset = (isSub) ? -Offset : Offset; in rewriteARMFrameIndex()
3319 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; in getNumMicroOpsSwiftLdSt() local
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| H A D | ARMISelLowering.cpp | 12184 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; in EmitInstrWithCustomInserter() local
12186 if (isSub) in EmitInstrWithCustomInserter()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 234 bool isSub = NumBytes < 0; in emitSPUpdate() local
235 uint64_t Offset = isSub ? -NumBytes : NumBytes; in emitSPUpdate()
237 isSub ? MachineInstr::FrameSetup : MachineInstr::FrameDestroy; in emitSPUpdate()
268 if (isSub && !isEAXLiveIn(MBB)) in emitSPUpdate()
274 unsigned AddSubRROpc = isSub ? getSUBrrOpcode(Uses64BitFramePtr) in emitSPUpdate()
300 if (isSub) in emitSPUpdate()
328 unsigned Reg = isSub ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) in emitSPUpdate()
331 unsigned Opc = isSub ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r) in emitSPUpdate()
334 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)) in emitSPUpdate()
341 BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue) in emitSPUpdate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 2605 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
2614 let Inst{30} = isSub;
2622 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
2624 : BaseBaseAddSubCarry<isSub, regtype, asm,
2627 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
2629 : BaseBaseAddSubCarry<isSub, regtype, asm,
2634 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
2636 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
2640 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
2646 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GenericMachineInstrs.h | 443 bool isSub() const { return !isAdd(); } in isSub() function
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 4366 bool isSub=false) { in tryEmitFMulAdd() argument
4408 return buildFMulAdd(LHSBinOp, op.RHS, CGF, Builder, NegLHS, isSub); in tryEmitFMulAdd()
4417 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub ^ NegRHS, false); in tryEmitFMulAdd()
4428 return buildFMulAdd(LHSBinOp, op.RHS, CGF, Builder, NegLHS, isSub); in tryEmitFMulAdd()
4438 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub ^ NegRHS, false); in tryEmitFMulAdd()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 4723 bool ProducesNegatedCarry = CarrySrcMI->isSub(); in emitCarryIn()
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