Lines Matching refs:isSub

2473 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
2482   let Inst{30}    = isSub;
2490 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
2492     : BaseBaseAddSubCarry<isSub, regtype, asm,
2495 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
2497     : BaseBaseAddSubCarry<isSub, regtype, asm,
2503 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
2505   def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
2509   def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
2515   def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
2520   def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
2599 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
2611   let Inst{15}    = isSub;
2617 multiclass MulAccum<bit isSub, string asm> {
2619   def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm, []>,
2624   def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm, []>,
2630 class WideMulAccum<bit isSub, bits<3> opc, string asm,
2632   : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
2788 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
2795   let Inst{30}    = isSub;
2802 class AddSubImmShift<bit isSub, bit setFlags, RegisterClass dstRegtype,
2805     : BaseAddSubImm<isSub, setFlags, dstRegtype, asm_inst, "\t$Rd, $Rn, $imm",
2821 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
2832   let Inst{30}    = isSub;
2845 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
2857   let Inst{30}    = isSub;
2871 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
2882   let Inst{30}    = isSub;
2903 multiclass AddSub<bit isSub, string mnemonic, string alias,
2912   def Wri  : AddSubImmShift<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
2917   def Xri  : AddSubImmShift<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
2927   def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
2931   def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
2939   def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
2943   def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
2949   def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
2984 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
2988   def Wri  : AddSubImmShift<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
2992   def Xri  : AddSubImmShift<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
3002   def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
3006   def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
3013   def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
3017   def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
3023   def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
3086 class AddSubG<bit isSub, string asm_inst, SDPatternOperator OpNode>
3088           isSub, 0, GPR64sp, asm_inst, "\t$Rd, $Rn, $imm6, $imm4",
5482 class BaseThreeOperandFPData<bit isNegated, bit isSub,
5494   let Inst{15}    = isSub;
5500 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
5502   def Hrrr : BaseThreeOperandFPData<isNegated, isSub, FPR16, asm,
5509   def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
5515   def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
12546 class BaseAddSubCPA<bit isSub, string asm> : I<(outs GPR64sp:$Rd),
12554   let Inst{30} = isSub;
12568 multiclass AddSubCPA<bit isSub, string asm> {
12569   def _shift : BaseAddSubCPA<isSub, asm>;
12573 class MulAccumCPA<bit isSub, string asm>
12574   : BaseMulAccum<isSub, 0b011, GPR64, GPR64, asm, []>, Sched<[]> {