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Searched refs:WriteRes (Results 1 – 25 of 80) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedTTAscalonD8.td46 def : WriteRes<WriteJmp, [AscalonFXC]>;
47 def : WriteRes<WriteJal, [AscalonFXC]>;
48 def : WriteRes<WriteJalr, [AscalonFXC]>;
51 def : WriteRes<WriteIALU32, [AscalonFX]>;
52 def : WriteRes<WriteIALU, [AscalonFX]>;
53 def : WriteRes<WriteShiftImm32, [AscalonFX]>;
54 def : WriteRes<WriteShiftImm, [AscalonFX]>;
55 def : WriteRes<WriteShiftReg32, [AscalonFX]>;
56 def : WriteRes<WriteShiftReg, [AscalonFX]>;
60 def : WriteRes<WriteIMul, [AscalonFXA]>;
[all …]
H A DRISCVSchedAndes45.td50 def : WriteRes<WriteIALU, [Andes45ALU]>;
51 def : WriteRes<WriteIALU32, [Andes45ALU]>;
52 def : WriteRes<WriteShiftImm, [Andes45ALU]>;
53 def : WriteRes<WriteShiftImm32, [Andes45ALU]>;
54 def : WriteRes<WriteShiftReg, [Andes45ALU]>;
55 def : WriteRes<WriteShiftReg32, [Andes45ALU]>;
58 def : WriteRes<WriteSFB, [Andes45ALU]> {
64 def : WriteRes<WriteJmp, [Andes45ALU]>;
65 def : WriteRes<WriteJal, [Andes45ALU]>;
66 def : WriteRes<WriteJalr, [Andes45ALU]>;
[all …]
H A DRISCVSchedGenericOOO.td55 def : WriteRes<WriteJmp, [GenericOOOBranch]>;
56 def : WriteRes<WriteJalr, [GenericOOOBranch]>;
57 def : WriteRes<WriteJal, [GenericOOOBranch]>;
62 def : WriteRes<WriteIALU, [GenericOOOALU]>;
63 def : WriteRes<WriteIALU32, [GenericOOOALU]>;
64 def : WriteRes<WriteShiftImm, [GenericOOOALU]>;
65 def : WriteRes<WriteShiftImm32, [GenericOOOALU]>;
66 def : WriteRes<WriteShiftReg, [GenericOOOALU]>;
67 def : WriteRes<WriteShiftReg32, [GenericOOOALU]>;
73 def : WriteRes<WriteIMul, [GenericOOOMulDiv]>;
[all …]
H A DRISCVSchedSiFiveP500.td47 def : WriteRes<WriteIALU, [SiFiveP500IntArith]>;
48 def : WriteRes<WriteIALU32, [SiFiveP500IntArith]>;
49 def : WriteRes<WriteShiftImm, [SiFiveP500IntArith]>;
50 def : WriteRes<WriteShiftImm32, [SiFiveP500IntArith]>;
51 def : WriteRes<WriteShiftReg, [SiFiveP500IntArith]>;
52 def : WriteRes<WriteShiftReg32, [SiFiveP500IntArith]>;
54 def : WriteRes<WriteJmp, [SiFiveP500Branch]>;
55 def : WriteRes<WriteJal, [SiFiveP500Branch]>;
56 def : WriteRes<WriteJalr, [SiFiveP500Branch]>;
68 def : WriteRes<WriteIMul, [SiFiveP500MulI2F]>;
[all …]
H A DRISCVSchedSpacemitX60.td52 def : WriteRes<WriteJmp, [SMX60_IEUA]>;
53 def : WriteRes<WriteJal, [SMX60_IEUA]>;
54 def : WriteRes<WriteJalr, [SMX60_IEUA]>;
58 def : WriteRes<WriteIALU32, [SMX60_IEU]>;
59 def : WriteRes<WriteIALU, [SMX60_IEU]>;
60 def : WriteRes<WriteShiftImm32, [SMX60_IEU]>;
61 def : WriteRes<WriteShiftImm, [SMX60_IEU]>;
62 def : WriteRes<WriteShiftReg32, [SMX60_IEU]>;
63 def : WriteRes<WriteShiftReg, [SMX60_IEU]>;
66 def : WriteRes<WriteIMul32, [SMX60_IEU]> { let Latency = 3; }
[all …]
H A DRISCVSchedXiangShanNanHu.td47 def : WriteRes<WriteJmp, [XS2MISC]>;
48 def : WriteRes<WriteJal, [XS2MISC]>;
49 def : WriteRes<WriteJalr, [XS2MISC]>;
53 def : WriteRes<WriteIALU, [XS2ALU]>;
54 def : WriteRes<WriteIALU32, [XS2ALU]>;
55 def : WriteRes<WriteShiftImm, [XS2ALU]>;
56 def : WriteRes<WriteShiftImm32, [XS2ALU]>;
57 def : WriteRes<WriteShiftReg, [XS2ALU]>;
58 def : WriteRes<WriteShiftReg32, [XS2ALU]>;
63 def : WriteRes<WriteIMul, [XS2MDU]>;
[all …]
H A DRISCVSchedMIPSP8700.td44 def : WriteRes<WriteIALU, [p8700WriteEitherALU]>;
45 def : WriteRes<WriteIALU32, [p8700WriteEitherALU]>;
46 def : WriteRes<WriteShiftImm, [p8700WriteEitherALU]>;
47 def : WriteRes<WriteShiftImm32, [p8700WriteEitherALU]>;
48 def : WriteRes<WriteShiftReg, [p8700WriteEitherALU]>;
49 def : WriteRes<WriteShiftReg32, [p8700WriteEitherALU]>;
52 def : WriteRes<WriteSHXADD, [p8700WriteEitherALU]>;
53 def : WriteRes<WriteSHXADD32, [p8700WriteEitherALU]>;
57 def : WriteRes<WriteCLZ, [p8700IssueAL2]>;
58 def : WriteRes<WriteCTZ, [p8700IssueAL2]>;
[all …]
H A DRISCVSchedSyntacoreSCR7.td29 def : WriteRes<WriteJmp, [BRU]>;
30 def : WriteRes<WriteJal, [BRU]>;
31 def : WriteRes<WriteJalr, [BRU]>;
36 def : WriteRes<WriteIALU, [ALU]>;
37 def : WriteRes<WriteIALU32, [ALU]>;
38 def : WriteRes<WriteShiftImm, [ALU]>;
39 def : WriteRes<WriteShiftImm32, [ALU]>;
40 def : WriteRes<WriteShiftReg, [ALU]>;
41 def : WriteRes<WriteShiftReg32, [ALU]>;
47 def : WriteRes<WriteIMul, Resources>;
[all …]
H A DRISCVSchedRocket.td51 def : WriteRes<WriteJmp, [RocketUnitB]>;
52 def : WriteRes<WriteJal, [RocketUnitB]>;
53 def : WriteRes<WriteJalr, [RocketUnitB]>;
56 def : WriteRes<WriteIALU32, [RocketUnitALU]>;
57 def : WriteRes<WriteIALU, [RocketUnitALU]>;
58 def : WriteRes<WriteShiftImm32, [RocketUnitALU]>;
59 def : WriteRes<WriteShiftImm, [RocketUnitALU]>;
60 def : WriteRes<WriteShiftReg32, [RocketUnitALU]>;
61 def : WriteRes<WriteShiftReg, [RocketUnitALU]>;
65 def : WriteRes<WriteIMul, [RocketUnitIMul]>;
[all …]
H A DRISCVSchedSyntacoreSCR345.td33 def : WriteRes<WriteJmp, [BRU]>;
34 def : WriteRes<WriteJal, [BRU]>;
35 def : WriteRes<WriteJalr, [BRU]>;
40 def : WriteRes<WriteIALU, [ALU]>;
41 def : WriteRes<WriteIALU32, [ALU]>;
42 def : WriteRes<WriteShiftImm, [ALU]>;
43 def : WriteRes<WriteShiftImm32, [ALU]>;
44 def : WriteRes<WriteShiftReg, [ALU]>;
45 def : WriteRes<WriteShiftReg32, [ALU]>;
51 def : WriteRes<WriteIMul, [MUL]>;
[all …]
H A DRISCVSchedSyntacoreSCR1.td41 def : WriteRes<WriteJmp, [SCR1_CFU]>;
42 def : WriteRes<WriteJal, [SCR1_CFU]>;
43 def : WriteRes<WriteJalr, [SCR1_CFU]>;
46 def : WriteRes<WriteIALU32, [SCR1_ALU]>;
47 def : WriteRes<WriteIALU, [SCR1_ALU]>;
48 def : WriteRes<WriteShiftImm32, [SCR1_ALU]>;
49 def : WriteRes<WriteShiftImm, [SCR1_ALU]>;
50 def : WriteRes<WriteShiftReg32, [SCR1_ALU]>;
51 def : WriteRes<WriteShiftReg, [SCR1_ALU]>;
54 def : WriteRes<WriteIMul, [SCR1_MUL]>;
[all …]
H A DRISCVSchedule.td259 def : WriteRes<WriteFAdd16, []>;
260 def : WriteRes<WriteFClass16, []>;
261 def : WriteRes<WriteFCvtI64ToF16, []>;
262 def : WriteRes<WriteFCvtI32ToF16, []>;
263 def : WriteRes<WriteFCvtF16ToI64, []>;
264 def : WriteRes<WriteFCvtF16ToI32, []>;
265 def : WriteRes<WriteFDiv16, []>;
266 def : WriteRes<WriteFCmp16, []>;
267 def : WriteRes<WriteFMA16, []>;
268 def : WriteRes<WriteFMinMax16, []>;
[all …]
H A DRISCVScheduleZb.td89 def : WriteRes<WriteSHXADD, []>;
90 def : WriteRes<WriteSHXADD32, []>;
99 def : WriteRes<WriteRotateImm, []>;
100 def : WriteRes<WriteRotateImm32, []>;
101 def : WriteRes<WriteRotateReg, []>;
102 def : WriteRes<WriteRotateReg32, []>;
103 def : WriteRes<WriteCLZ, []>;
104 def : WriteRes<WriteCLZ32, []>;
105 def : WriteRes<WriteCTZ, []>;
106 def : WriteRes<WriteCTZ32, []>;
[all …]
H A DRISCVSchedSiFiveP800.td118 def : WriteRes<WriteIALU, [SiFiveP800IntArith]>;
119 def : WriteRes<WriteIALU32, [SiFiveP800IntArith]>;
120 def : WriteRes<WriteShiftImm, [SiFiveP800IntArith]>;
121 def : WriteRes<WriteShiftImm32, [SiFiveP800IntArith]>;
122 def : WriteRes<WriteShiftReg, [SiFiveP800IntArith]>;
123 def : WriteRes<WriteShiftReg32, [SiFiveP800IntArith]>;
125 def : WriteRes<WriteJmp, [SiFiveP800Branch]>;
126 def : WriteRes<WriteJal, [SiFiveP800Branch]>;
127 def : WriteRes<WriteJalr, [SiFiveP800Branch]>;
138 def : WriteRes<WriteIMul, [SiFiveP800Mul]>;
[all …]
H A DRISCVSchedSiFiveP400.td180 def : WriteRes<WriteIALU, [SiFiveP400IntArith]>;
181 def : WriteRes<WriteIALU32, [SiFiveP400IntArith]>;
182 def : WriteRes<WriteShiftImm, [SiFiveP400IntArith]>;
183 def : WriteRes<WriteShiftImm32, [SiFiveP400IntArith]>;
184 def : WriteRes<WriteShiftReg, [SiFiveP400IntArith]>;
185 def : WriteRes<WriteShiftReg32, [SiFiveP400IntArith]>;
187 def : WriteRes<WriteJmp, [SiFiveP400Branch]>;
188 def : WriteRes<WriteJal, [SiFiveP400Branch]>;
189 def : WriteRes<WriteJalr, [SiFiveP400Branch]>;
201 def : WriteRes<WriteIMul, [SiFiveP400MulDiv]>;
[all …]
H A DRISCVSchedSiFive7.td266 def : WriteRes<WriteJmp, [PipeB]>;
267 def : WriteRes<WriteJal, [PipeB]>;
268 def : WriteRes<WriteJalr, [PipeB]>;
272 def : WriteRes<WriteSFB, [PipeA, PipeB]> {
279 def : WriteRes<WriteIALU, [PipeAB]>;
280 def : WriteRes<WriteIALU32, [PipeAB]>;
281 def : WriteRes<WriteShiftImm, [PipeAB]>;
282 def : WriteRes<WriteShiftImm32, [PipeAB]>;
283 def : WriteRes<WriteShiftReg, [PipeAB]>;
284 def : WriteRes<WriteShiftReg32, [PipeAB]>;
[all …]
H A DRISCVSchedSiFiveP600.td358 def : WriteRes<WriteIALU, [SiFiveP600IntArith]>;
359 def : WriteRes<WriteIALU32, [SiFiveP600IntArith]>;
360 def : WriteRes<WriteShiftImm, [SiFiveP600IntArith]>;
361 def : WriteRes<WriteShiftImm32, [SiFiveP600IntArith]>;
362 def : WriteRes<WriteShiftReg, [SiFiveP600IntArith]>;
363 def : WriteRes<WriteShiftReg32, [SiFiveP600IntArith]>;
365 def : WriteRes<WriteJmp, [SiFiveP600Branch]>;
366 def : WriteRes<WriteJal, [SiFiveP600Branch]>;
367 def : WriteRes<WriteJalr, [SiFiveP600Branch]>;
378 def : WriteRes<WriteIMul, [SiFiveP600MulI2F]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td70 // These WriteRes entries are not used in the Falkor sched model.
71 def : WriteRes<WriteImm, []> { let Unsupported = 1; }
72 def : WriteRes<WriteI, []> { let Unsupported = 1; }
73 def : WriteRes<WriteISReg, []> { let Unsupported = 1; }
74 def : WriteRes<WriteIEReg, []> { let Unsupported = 1; }
75 def : WriteRes<WriteExtr, []> { let Unsupported = 1; }
76 def : WriteRes<WriteIS, []> { let Unsupported = 1; }
77 def : WriteRes<WriteID32, []> { let Unsupported = 1; }
78 def : WriteRes<WriteID64, []> { let Unsupported = 1; }
79 def : WriteRes<WriteIM3
[all...]
H A DAArch64SchedKryo.td66 def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }
67 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
68 def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]>
70 def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]>
72 def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]>
74 def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }
75 def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]>
77 def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]>
79 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
80 def : WriteRes<WriteIM6
[all...]
H A DAArch64SchedThunderX.td52 def : WriteRes<WriteImm, [THXT8XUnitALU]> { let Latency = 1; }
53 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
54 def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; }
55 def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; }
56 def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; }
57 def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
60 def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
65 def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
71 def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
76 def : WriteRes<WriteID6
[all...]
H A DAArch64SchedA53.td61 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
62 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
63 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
64 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
65 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
66 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
69 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
70 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
73 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
74 def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td67 def : WriteRes<SchedRW, ExePorts> {
75 def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
84 def : WriteRes<WriteRMW, [SLM_MEC_RSV]> { let NumMicroOps = 0; }
86 def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
87 def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
88 def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; }
89 def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
90 def : WriteRes<WriteZero, []>;
139 def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
140 def : WriteRes<WriteSETCCStor
[all...]
H A DX86SchedLunarlakeP.td66 // Workaround to represent invalid ports. WriteRes shouldn't use this resource.
129 def : WriteRes<SchedRW, ExePorts> {
137 def : WriteRes<SchedRW.Folded, !listconcat([LNLPPort20_21_22], ExePorts)> {
150 def : WriteRes<WriteADC, [LNLPPort00_02_04]>;
152 def : WriteRes<WriteAESDecEnc, [LNLPVPort00_01]> {
159 def : WriteRes<WriteALU, [LNLPPort01_03_05]>;
160 def : WriteRes<WriteALULd, [LNLPPort01_03_05, LNLPPort20_21_22]> {
164 def : WriteRes<WriteBLS, [LNLPPort01_03_05]>;
168 def : WriteRes<WriteBSWAP32, [LNLPPort01_03_05]>;
171 def : WriteRes<WriteBitTestSet, [LNLPPort01_03_05]>;
[all …]
H A DX86ScheduleAtom.td63 def : WriteRes<SchedRW, RRPorts> {
70 def : WriteRes<SchedRW.Folded, RMPorts> {
78 def : WriteRes<WriteRMW, [AtomPort0]>;
122 def : WriteRes<WriteSETCC, [AtomPort01]>;
123 def : WriteRes<WriteSETCCStore, [AtomPort01]> {
127 def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
139 def : WriteRes<WriteLEA, [AtomPort1]>;
171 def : WriteRes<WriteLoad, [AtomPort0]>;
172 def : WriteRes<WriteStore, [AtomPort0]>;
173 def : WriteRes<WriteStoreN
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM7.td56 def : WriteRes<WriteALU, [M7UnitALU]> { let Latency = 1; }
60 def : WriteRes<WriteALUsi, [M7UnitALU, M7UnitShift1]>;
61 def : WriteRes<WriteALUsr, [M7UnitALU, M7UnitShift1]>;
62 def : WriteRes<WriteALUSsr, [M7UnitALU, M7UnitShift1]>;
66 def : WriteRes<WriteCMP, [M7UnitALU]> { let Latency = 1; }
67 def : WriteRes<WriteCMPsi, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
68 def : WriteRes<WriteCMPsr, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
72 def : WriteRes<WriteMUL16, [M7UnitMAC]>;
73 def : WriteRes<WriteMUL32, [M7UnitMAC]>;
74 def : WriteRes<WriteMUL64Lo, [M7UnitMAC]>;
[all …]

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